Datasheet

LPC Interface (D31:F0)
Intel
®
Atom™ Processor E6xx Series Datasheet
197
10.5.2 BDE—BIOS Decode Enable
27 : 24 0h RW IF0
F0-F7 IDSEL: IDSEL to use in FWH cycle for range enabled by
BDE.EF0. The Address ranges are: FFF00000h – FFF7FFFFh,
FFB00000h – FFB7FFFFh
23 : 20 1h RW IE8
E8-EF IDSEL: IDSEL to use in FWH cycle for range enabled by
BDE.EE8. The Address ranges are: FFE80000h – FFEFFFFFh,
FFA80000h – FFAFFFFFh
19 : 16 1h RW IE0
E0-E7 IDSEL: IDSEL to use in FWH cycle for range enabled by
BDE.EE0. The Address ranges are: FFE00000h – FFE7FFFFh,
FFA00000h – FFA7FFFFh
15 : 12 2h RW ID8
D8-DF IDSEL: IDSEL to use in FWH cycle for range enabled by
BDE.ED8. The Address ranges are: FFD80000h – FFDFFFFFh,
FF980000h – FF9FFFFFh
11 : 08 2h RW ID0
D0-D7 IDSEL: IDSEL to use in FWH cycle for range enabled by
BDE.ED0. The Address ranges are: FFD00000h – FFD7FFFFh,
FF900000h – FF97FFFFh
07 : 04 3h RW IC8
C8-CF IDSEL: IDSEL to use in FWH cycle for range enabled by
BDE.EC8. The Address ranges are: FFC80000h – FFCFFFFFh,
FF880000h – FF8FFFFFh
03 : 00 3h RW IC0
C0-C7 IDSEL: IDSEL to use in FWH cycle for range enabled by
BDE.EC0. The Address ranges are: FFC00000h – FFC7FFFFh,
FF800000h – FF87FFFFh
Table 294. Offset D4h: BDE – BIOS Decode Enable (Sheet 1 of 2)
Size: 32 bit Default: FF000000h Power Well:
Access
PCI Configuration B:D:F X:31:0
Offset Start:
Offset End:
D4h
D7h
Bit Range Default Access Acronym Description
31 1b RO EF8
F8-FF Enable: Enables decoding of BIOS range FFF80000h –
FFFFFFFFh and FFB80000h – FFBFFFFFh.
0 = Disable
1 = Enable
30 1b RW EF0
F0-F8 Enable: Enables decoding of BIOS range FFF00000h –
FFF7FFFFh and FFB00000h – FFB7FFFFh.
0 = Disable
1 = Enable
29 1b RW EE8
E8-EF Enable: Enables decoding of BIOS range FFE80000h –
FFEFFFFFh and FFA80000h - FFAFFFFFh
0 = Disable
1 = Enable
28 1b RW EE0
E0-E8 Enable: Enables decoding of BIOS range FFE00000h –
FFE7FFFFh and FFA00000h – FFA7FFFFh.
0 = Disable
1 = Enable
Table 293. Offset D0h: FS – FWH ID Select (Sheet 2 of 2)
Size: 32 bit Default: 00112233h Power Well:
Access
PCI Configuration B:D:F X:31:0
Offset Start:
Offset End:
D0h
D3h
Bit Range Default Access Acronym Description