Datasheet

LPC Interface (D31:F0)
Intel
®
Atom™ Processor E6xx Series Datasheet
196
10.4.2 SCNT—Serial IRQ Control Register
10.4.3 WDTBA-WDT Base Address
10.5 FWH Configuration Registers
10.5.1 FS—FWH ID Select Register
This register contains the IDSEL fields the LPC Bridge uses for memory cycles going to
the FWH.
Note: The usage of FWH will not be validated or supported.
Table 291. Offset 68h: SCNT – Serial IRQ Control
Size: 8 bit Default: 80h Power Well:
Access
PCI Configuration B:D:F X:31:0
Offset Start:
Offset End:
68h
6Bh
Bit Range Default Access Acronym Description
07 0 RW MD
Mode:
This bit must be set to ensure that the first action of the processor is a
start frame.
0 = Processor is in quiet mode
1 = Processor is in continuous mode
06 : 00 00h RO RSVD Reserved
Table 292. Offset 84h: WDTBA – WDT Base Address
Size: 32 bit Default: 00000000h Power Well:
Access
PCI Configuration B:D:F X:31:0
Offset Start:
Offset End:
84h
87h
Bit Range Default Access Acronym Description
31 0 RW RW
Enable: When set, decode of the IO range pointed to by the BA is
enabled.
30 : 16 0h RO Reserved. Always 0
15 : 06 0h RW Base Address: Provides the 64 bytes of I/O space for WDT.
05 : 00 0h RO RO Reserved.
Table 293. Offset D0h: FS – FWH ID Select (Sheet 1 of 2)
Size: 32 bit Default: 00112233h Power Well:
Access
PCI Configuration B:D:F X:31:0
Offset Start:
Offset End:
D0h
D3h
Bit Range Default Access Acronym Description
31 : 28 0h RO IF8
F8-FF IDSEL: IDSEL to use in FWH cycle for range enabled by
BDE.EF8. The Address ranges are: FFF80000h – FFFFFFFFh,
FFB80000h – FFBFFFFFh and 000E0000h – 000FFFFFh