Datasheet

LPC Interface (D31:F0)
Intel
®
Atom™ Processor E6xx Series Datasheet
195
10.4 Interrupt Control
10.4.1 PxRC—PIRQx Routing Control Register
Offset 60h routes PIRQA, 61h routes PIRQB, 62h routes PIRQC, 63h routes PIRQD, 64h
routes PIRQE, 65h routes PIRQF, 66h routes PIRQG, and 67h routes PIRQH.
02 0 RW D8259
Disable 8259: When set, decodes to the 8259 will be disabled, and
the accesses instead will be sent to LPC. This allows testing to
determine whether these functions are needed for XP and Vista.
01 0 RW D8254
Disable 8254: When set, decodes to the 8254 will be disabled, and
the accesses instead will be sent to LPC. This allows testing to
determine whether these functions are needed for XP and Vista.
00 0 RW RSVD Reserved
Table 289. Offset 5Ch: MC – Miscellaneous Control (Sheet 3 of 3)
Size: 32 bit Default: 00000000h Power Well:
Access
PCI Configuration B:D:F X:31:0
Offset Start:
Offset End:
5Ch
5Fh
Bit Range Default Access Acronym Description
Table 290. Offset 60h – 67h: PxRC – PIRQ[A-H] Routing Control
Size: 8 bit Default: 80h Power Well:
Access
PCI Configuration B:D:F X:31:0
Offset Start:
Offset End:
60h
67h
Bit Range Default Access Acronym Description
07 1 RW REN
Interrupt Routing Enable (REN):
0 = The corresponding PIRQ is routed to one of the legacy interrupts
specified in bits[3:0].
1 = The PIRQ is not routed to the 8259.
Note: BIOS must program this bit to 0 during POST for any of the
PIRQs that are being used. The value of this bit may
subsequently be changed by the OS when setting up for I/O
APIC interrupt delivery mode.
06 : 04 000b RO RSVD Reserved
03 : 00 0 RW IR
IRQ Routing: Indicates how to route PIRQx_B
Bits Mapping Bits Mapping
0h Reserved 8h Reserved
1h Reserved 9h IRQ9
2h Reserved Ah IRQ10
3h IRQ3 Bh IRQ11
4h IRQ4 Ch IRQ12
5h IRQ5 Dh Reserved
6h IRQ6 Eh IRQ14
7h IRQ7 Fh IRQ15