Datasheet

LPC Interface (D31:F0)
Intel
®
Atom™ Processor E6xx Series Datasheet
194
23 : 21 0h RO RSVD Reserved
20 0 RW BTC6
Block Timer Ticks in C6: When set, timer ticks will be blocked up to
NTT while the processor is in the C6 state. If not set, timer ticks will
not be blocked in the C6 state.
31 : 29 0h RW RSVD Reserved
19 0 RW BTC5
Block Timer Ticks in C5: Same definition as BTC6, but for the C5
state.
18 0 RW BTC4
Block Timer Ticks in C4: Same definition as BTC6, but for the C4
state.
17 0 RW BTC3
Block Timer Ticks in C3: Same definition as BTC6, but for the C3
state.
16 0 RW BTC2
Block Timer Ticks in C2: Same definition as BTC6, but for the C2
state.
15 : 13 0h RO Reserved
12 0 RW BIC6
Block Interrupts in C6: When set, interrupts will be blocked while
the processor is in the C6 state, until a timer tick occurs. If not set,
interrupts will not be blocked in the C6 state. Blocking may occur for
NTT timer ticks if BTC6 is set.
11 0 RW BIC5
Block Interrupts in C5: Same definition as BIC6, but for the C5
state.
10 0 RW BIC4
Block Interrupts in C4: Same definition as BIC6, but for the C4
state.
09 0 RW BIC3
Block Interrupts in C3: Same definition as BIC6, but for the C3
state.
08 0 RW BIC2
Block Interrupts in C2: Same definition as BIC6, but for the C2
state.
07 Strap RO MEMID3
Bootstrap MEMID3: Bootstrap for memory controller configuration
ID3.
Defines the number of ranks enabled.
1: 1 Rank
0: 2 Rank
06 Strap RO MEMID2
Bootstrap MEMID2: Bootstrap for memory controller configuration
ID2.
Defines the memory device densities that the processor is connected
to.
[MEMID2: MEMID1]
11: 2 Gb
10: 1 Gb
01: 512 Mb
00: 256 Mb
05 Strap RO MEMID1
Bootstrap MEMID1: Bootstrap for memory controller configuration
ID1.
Defines the memory device densities that the processor is connected
to.
Please refer to MEMID2.
04 Strap RO MEMID0
Bootstrap MEMID0: Bootstrap for memory controller configuration
ID0.
Defines the memory device width:
0: x16 devices
1: x8 devices
03 0 RW DRTC
Disable RTC: When set, decodes to the RTC will be disabled, and the
accesses instead will be sent to LPC. This allows testing to determine
whether these functions are needed for XP and Vista.
Table 289. Offset 5Ch: MC – Miscellaneous Control (Sheet 2 of 3)
Size: 32 bit Default: 00000000h Power Well:
Access
PCI Configuration B:D:F X:31:0
Offset Start:
Offset End:
5Ch
5Fh
Bit Range Default Access Acronym Description