Datasheet

LPC Interface (D31:F0)
Intel
®
Atom™ Processor E6xx Series Datasheet
192
10.3.4 GPE0BLK—GPE0_BLK Base Address Register
10.3.5 LPCS—LPC Clock Strength Control Register
The LPC Clock 2 and 1 are controlled via the SoftStrap software.
03 : 00 0h RO RSVD Reserved.
Table 286. Offset 4Ch: GPE0BLK – GPE0_BLK Base Address
Size: 32 bit Default: 00000000h Power Well:
Access
PCI Configuration B:D:F X:31:0
Offset Start:
Offset End:
4Ch
4Fh
Bit Range Default Access Acronym Description
31 0 RW EN
Enable:
1 = Decode of the IO range pointed to by the GPE0BASE.BA is
enabled.
30 : 16 0h RO RSVD Reserved.
15 : 06 0h RW BA
Base Address: This field provides the 64 bytes of I/O space for
GPE0_BLK.
05 : 00 0h RO RSVD Reserved.
Table 285. Offset 48h: PM1BLK – PM1_BLK Base Address (Sheet 2 of 2)
Size: 32 bit Default: 00000000h Power Well:
Access
PCI Configuration B:D:F X:31:0
Offset Start:
Offset End:
48h
4Bh
Bit Range Default Access Acronym Description
Table 287. Offset 54h: LPCS – LPC Clock Strength Control (Sheet 1 of 2)
Size: 32 bit Default: Power Well:
Access
PCI Configuration B:D:F X:31:0
Offset Start:
Offset End:
54h
57h
Bit Range Default Access Acronym Description
31 : 19 0h RO RSVD Reserved.
18 1b RW C2EN
Clock 2 Enable:
1 = Enabled.
0 = Disabled.
17 1b RW C1EN
Clock 1 Enable:
1 = Enabled.
0 = Disabled.
16 : 06 0h RO RSVD Reserved
05 1b RW C22M Clock 2 2m Strength: Clock 2 2m Strength Control
04 1b RW C24M Clock 2 4m Strength: Clock 2 4m Strength Control
03 1b RW C12M Clock 1 2m Strength: Clock 1 2m Strength Control
02 1b RW C14M Clock 1 4m Strength: Clock 1 4m Strength Control
01 1b RW C02M Clock 0 2m Strength: Clock 0 2m Strength Control