Datasheet
LPC Interface (D31:F0)
Intel
®
Atom™ Processor E6xx Series Datasheet
191
10.3 ACPI Device Configuration
10.3.1 SMBA—SMBus Base Address Register
10.3.2 GBA—GPIO Base Address Register
10.3.3 PM1BLK—PM1_BLK Base Address Register
Table 283. Offset 40h: SMBA – SMBus Base Address
Size: 32 bit Default: 00000000h Power Well:
Access
PCI Configuration B:D:F X:31:0
Offset Start:
Offset End:
40h
43h
Bit Range Default Access Acronym Description
31 0 RW EN
Enable:
1 = Decode of the I/O range pointed to by the SMBASE.BA field is
enabled.
30 : 16 0h RO RSVD Reserved.
15 : 06 0h RW BA
Base Address: This field provides the 64 bytes of I/O space for
SMBus
05 : 00 0h RO RSVD Reserved.
Table 284. Offset 44h: GBA – GPIO Base Address
Size: 32 bit Default: 00000000h Power Well:
Access
PCI Configuration B:D:F X:31:0
Offset Start:
Offset End:
44h
47h
Bit Range Default Access Acronym Description
31 0 RW EN
Enable:
1 = Decode of the I/O range pointed to by the GPIOBASE.BA is
enabled.
30 : 16 0h RO RSVD Reserved.
15 : 06 0h RW BA Base Address: This field provides the 64 bytes of I/O space for GPIO.
05 : 00 0h RO RSVD Reserved.
Table 285. Offset 48h: PM1BLK – PM1_BLK Base Address (Sheet 1 of 2)
Size: 32 bit Default: 00000000h Power Well:
Access
PCI Configuration B:D:F X:31:0
Offset Start:
Offset End:
48h
4Bh
Bit Range Default Access Acronym Description
31 0 RW EN
Enable:
1 = Decode of the I/O range pointed to by the PM1BASE.BA is enabled.
30 : 16 0h RO RSVD Reserved.
15 : 04 0h RW BA
Base Address: This field provides the 64 bytes of I/O space for
PM1_BLK.