Datasheet

LPC Interface (D31:F0)
Intel
®
Atom™ Processor E6xx Series Datasheet
190
10.2.5 CC—Class Code Register
10.2.6 HDTYPE—Header Type Register
10.2.7 SS—Subsystem Identifiers Register
This register is initialized to logic 0 by the assertion of RESET_B. This register can be
written only once after RESET_B de-assertion.
Table 280. Offset 09h: CC – Class Code
Size: 24 bit Default: 060100h Power Well:
Access
PCI Configuration B:D:F X:31:0
Offset Start:
Offset End:
09h
0Bh
Bit Range Default Access Acronym Description
23 : 16 06h RO BCC Base Class Code: Indicates the device is a bridge device.
15 : 08 01h RO SCC Sub-Class Code: Indicates the device a PCI to ISA bridge.
07 : 00 00h RO PI
Programming Interface: The LPC bridge has no programming
interface.
Table 281. Offset 0Eh: HDTYPE – Header Type
Size: 8 bit Default: 80h Power Well:
Access
PCI Configuration B:D:F X:31:0
Offset Start:
Offset End:
0Eh
0Eh
Bit Range Default Access Acronym Description
07 1 RO MFD
Multi-function Device: This bit is ‘1’ to indicate a multi-function
device.
06 : 00 00h RO HTYPE Header Type: Identifies the header layout is a generic device.
Table 282. Offset 2Ch: SS – Subsystem Identifiers
Size: 32 bit Default: 00000000h Power Well:
Access
PCI Configuration B:D:F X:31:0
Offset Start:
Offset End:
2Ch
2Fh
Bit Range Default Access Acronym Description
31 : 16 0000h RWO SSID Subsystem ID: This is written by BIOS. No hardware action is taken.
15 : 00 0000h RWO SSVID
Subsystem Vendor ID: This is written by BIOS. No hardware action
is taken.