Datasheet

Contents
Intel
®
Atom™ Processor E6xx Series Datasheet
19
318 21h, A1h: ICW4 – Initialization Command Word 4 Register.......................................... 215
319 21h, A1h: OCW1 – Operational Control Word 1 (Interrupt Mask) .................................. 216
320 20h, A0h: OCW2 – Operational Control Word 2 .......................................................... 216
321 20h, A0h: OCW3 – Operational Control Word 3 .......................................................... 217
322 4D0h: ELCR1 – Master Edge/Level Control................................................................. 217
323 4D1h: ELCR2 – Slave Edge/Level Control .................................................................. 218
324 Content of Interrupt Vector Byte.............................................................................. 219
325 APIC Registers....................................................................................................... 223
326 Index Registers ..................................................................................................... 224
327 00h: ID – Identification Register .............................................................................. 224
328 01h: VS – Version Register...................................................................................... 224
329 10-11h – 3E-3Fh: RTE[0-23] – Redirection Table Entry ............................................... 225
330 Interrupt Delivery Address Value.............................................................................. 226
331 Interrupt Delivery Data Value .................................................................................. 227
332 Serial Interrupt Mode Selection................................................................................ 228
333 Data Frame Format................................................................................................ 229
334 RTC Registers........................................................................................................ 230
335 RTC Indexed Registers............................................................................................ 231
336 0Ah: Register A ..................................................................................................... 231
337 0Bh: Register B - General Configuration.................................................................... 232
338 0Ch: Register C - Flag Register................................................................................ 233
339 0Dh: Register D - Flag Register (RTC Well)................................................................ 233
340 GPIO I/O Register .................................................................................................. 234
341 00h: CGEN – Core Well GPIO Enable......................................................................... 234
342 04h: CGIO – Core Well GPIO Input/Output Select....................................................... 235
343 08h: CGLVL – Core Well GPIO Level for Input or Output.............................................. 235
344 0Ch: CGTPE – Core Well GPIO Trigger Positive Edge Enable......................................... 235
345 10h: CGTNE – Core Well GPIO Trigger Negative Edge Enable ....................................... 236
346 14h: CGGPE – Core Well GPIO GPE Enable ................................................................ 236
347 18h: CGSMI – Core Well GPIO SMI Enable................................................................. 236
348 1Ch: CGTS – Core Well GPIO Trigger Status .............................................................. 237
349 Resume Well GPIO Registers ................................................................................... 237
350 20h: RGEN – Resume Well GPIO Enable.................................................................... 237
351 24h: RGIO – Resume Well GPIO Input/Output Select.................................................. 238
352 28h: RGLVL – Resume Well GPIO Level for Input or Output ......................................... 238
353 2Ch: RGTPE – Resume Well GPIO Trigger Positive Edge Enable .................................... 239
354 30h: RGTNE – Resume Well GPIO Trigger Negative Edge Enable................................... 239
355 34h: RGGPE – Resume Well GPIO GPE Enable............................................................ 239
356 38h: RGSMI – Resume Well GPIO SMI Enable ............................................................ 240
357 3Ch: RGTS – Resume Well GPIO Trigger Status.......................................................... 240
358 SMBus Controller Registers...................................................................................... 241
359 00h: HCTL - Host Control Register............................................................................ 241
360 01h: HSTS - Host Status Register............................................................................. 242
361 02h: HCLK – Host Clock Divider ............................................................................... 243
362 04h: TSA - Transmit Slave Address .......................................................................... 243
363 05h: HCMD - Command Register.............................................................................. 243
364 06h: HD0 - Host Data 0 .......................................................................................... 244
365 07h: HD1 - Host Data 1 .......................................................................................... 244
366 20h – 3Fh: HBD – Host Block Data........................................................................... 244
367 SMBus Timings...................................................................................................... 245
368 SPI Pin Interface.................................................................................................... 246
369 GPIO Boot Source Selection..................................................................................... 247
370 Instructions........................................................................................................... 248
371 SPI Cycle Timings .................................................................................................. 249
372 Bus 0, Device 31, Function 0, PCI Register Mapped Through RCBA BAR......................... 250