Datasheet

LPC Interface (D31:F0)
Intel
®
Atom™ Processor E6xx Series Datasheet
189
10.2.2 CMD—Device Command Register
10.2.3 STS—Device Status Register
10.2.4 RID—Revision ID Register
15 : 00 8086h RO VID Vendor Identification: This is a 16-bit value assigned to Intel.
Table 277. Offset 04h: CMD – Device Command
Size: 16 bit Default: 0003h Power Well:
Access
PCI Configuration B:D:F X:31:0
Offset Start:
Offset End:
04h
05h
Bit Range Default Access Acronym Description
15 : 02 0 RO RSVD Reserved
01 1 RO MSE Memory Space Enable: Memory space cannot be disabled on LPC.
Table 278. Offset 06h: STS – Device Status
Size: 16 bit Default: 0000h Power Well:
Access
PCI Configuration B:D:F X:31:0
Offset Start:
Offset End:
06h
07h
Bit Range Default Access Acronym Description
15 : 00 0 RO RSVD Reserved
Table 279. Offset 08h: RID – Revision ID
Size: 8 bit Default: Refer to bit description Power Well:
Access
PCI Configuration B:D:F 0:31:0
Offset Start:
Offset End:
08h
08h
Bit Range Default Access Acronym Description
07 : 00
Refer to
bit
descript
ion
RWO RID
Revision ID: Refer to the Intel
®
Atom™ Processor E6x5C Series
Specification Update for the value of the Revision ID Register. For the
B-0 Stepping, this value is 01h. For the B-1 Stepping, this value is
02h.
Table 276. Offset 00h: ID – Identifiers (Sheet 2 of 2)
Size: 32 bit Default: 81868086h Power Well:
Access
PCI Configuration B:D:F X:31:0
Offset Start:
Offset End:
00h
03h
Bit Range Default Access Acronym Description