Datasheet

LPC Interface (D31:F0)
Intel
®
Atom™ Processor E6xx Series Datasheet
188
Note: By default, the LPC clocks are only active when LPC bus transfers occur. Because of this
behavior, LPC clocks must be routed directly to the bus devices; they cannot go
through a clock buffer or other circuit that could delay the signal going to the end
device.
10.2 PCI Configuration Registers
Note: Address locations that are not shown should be treated as Reserved.
.
10.2.1 ID—Identifiers
Table 275. LPC Interface PCI Register Address Map
Offset Mnemonic Register Name Default Type
00h-03h ID Identifiers 81868086h RO
04h–05h CMD Device Command 0003h RO
06h–07h STS Device Status 0000h RO
08h RID Revision Identification
01h (for B-0
stepping)
02h (for B-1
stepping)
RO
09h–0Bh CC Class Codes 060100h RO
0Eh HDTYPE Header Type 80h RO
2Ch–2Fh SS Subsystem Identifiers 00000000h R/WO
40h–43h SMBA SMBus Base Address 00000000h RO, R/W
44h–47h GBA GPIO Base Address 00000000h R/W, RO
48h–4Bh PM1BLK PM1_BLK Base Address 00000000h RO/ R/W
4Ch–4Fh GPE0BLK GPE0_BLK Base Address 00000000h RO, R/W
54h–57h LPCS LPC Clock Strength Control See description RO, R/W
58h–5Bh ACTL ACPI Control 00000003h RO, R/W
5Ch–5Fh MC Miscellaneous Control 00000000h RO, R/W
60h–67h PxRC PIRQ[A-H] Routing Control 80h RO, R/W
68h-6Bhh SCNT Serial IRQ Control 00h R/W, RO
84h-87h WDTBA WDT Base Address 00000000h R/W, RO
D0h–D3h FS FWH ID Select 00112233h RO, R/W
D4h-D7h BDE BIOS Decode Enable FF000000h RO, R/W
D8h-DBh BC BIOS Control 00000100h RO, R/W
F0h-F3h RCBA Root Complex Base Address 00000000h R/W, RO
Table 276. Offset 00h: ID – Identifiers (Sheet 1 of 2)
Size: 32 bit Default: 81868086h Power Well:
Access
PCI Configuration B:D:F X:31:0
Offset Start:
Offset End:
00h
03h
Bit Range Default Access Acronym Description
31 : 16 8186h RO DID Device Identification: PCI device ID for LPC