Datasheet

LPC Interface (D31:F0)
Intel
®
Atom™ Processor E6xx Series Datasheet
187
10.0 LPC Interface (D31:F0)
10.1 Functional Overview
The LPC controller implements a low pin count interface that supports the LPC 1.1
specification:
• LSMI_B can be connected to any of the SMI capable GPIO signals.
• The EC’s PME_B should connect it to GPE_B.
• The LPC controller’s SUS_STAT_B signal is connected directly to the LPCPD_B
signal.
The LPC controller does not implement DMA or bus mastering cycles.
The LPC bridge function resides in PCI Device 31:Function 0. This function contains
many other functional units, such as DMA and Interrupt controllers, Timers, Power
Management, System Management, GPIO, RTC, and LPC Configuration Registers. This
section contains the PCI configuration registers for the primary LPC interface. Power
Management details are found in a separate chapter, and other ACPI functions (RTC,
SMBus, GPIO, Interrupt controllers, Timers, etc.) can be found in the ACPI chapter.
10.1.1 Memory Cycle Notes
For cycles below 16M, the LPC Controller will perform standard LPC memory cycles. For
cycles targeting firmware, firmware memory cycles are used. Only 8-bit transfers are
performed. If a larger transfer appears, the LPC controller will break it into multiple
8-bit transfers until the request is satisfied.
If the cycle is not claimed by any peripheral (and subsequently aborted), the LPC
Controller will return a value of all 1’s to the processor.
10.1.2 Intel
®
Trusted Platform Module
ε
1.2 Support
The LPC interface supports accessing Intel
®
Trusted Platform Module
ε
(Intel
®
TPM
ε
) 1.2
devices by LPC Intel
®
TPM
ε
START encoding. Memory addresses within the range
FED40000h to FED4BFFFh will be accepted by the LPC bridge and sent on LPC as Intel
®
TPM
ε
special cycles. No additional checking of the memory cycle is performed.
10.1.3 FWH Cycle Notes
If the LPC controller receives any SYNC returned from the device other than short wait
(0101), long wait (0110), or ready (0000) when running a FWH cycle, indeterminate
results may occur. A FWH device is not allowed to assert an Error SYNC. The usage of
FWH will not be validated or supported.
10.1.4 LPC Output Clocks
The processor provides three output clocks to drive external LPC devices that may
require a PCI-like clock (33 MHz). The LPC output clocks operate at 1/4th the frequency
of H_CLKIN[P/N].
LPC_CLKOUT0 is the first clock to be used in the system, configuring its drive strength
is done by a strapping option on the GPIO4 pin. The buffer strengths of LPC_CLKOUT1
and LPC_CLKOUT2 default to 2-loads per clock and can be reprogrammed through LPC
configuration space.