Datasheet

Intel
®
High Definition Audio
β
D27:F0
Intel
®
Atom™ Processor E6xx Series Datasheet
185
9.3.2.1.47 Offset 1030h: EM2 – Extended Mode 2 Register
9.3.2.1.48 Offset 2030h: WLCLKA – Wall Clock Alias Register
Table 272. 1030h: EM2 – Extended Mode 2 Register
Size: 32 bit Default: 0000_0000h Power Well: Core
Access
PCI Configuration B:D:F 0:27:0
Offset Start:
Offset End:
1030h
1033h
Memory Mapped IO BAR: Offset:
Bit Range Default Access Acronym Description
31 :09 0 RO RSVD Reserved
08 0 RW CORBRPDIS
CORB Reset Pointer Change Disable: When this bit is 0 the CORB
Reset Pointer Reset works as described. When this bit is set to 1 the
CORB FIFO is not reset and the CORB Reset Pointer Reset bit is Write
Only and always read as 0.
07 :00 0 RO RSVD Reserved
Table 273. 2030h: WLCLKA – Wall Clock Alias Register
Size: 32 bit Default: 0000_0000h Power Well: Core
Access
PCI Configuration B:D:F 0:27:0
Offset Start:
Offset End:
2030h
2033h
Memory Mapped IO BAR: Offset:
Bit Range Default Access Acronym Description
31 :00 0 RO CounterA
Wall Clock Counter Alias: This is an alias of the WALCK register. 32 bit
counter that is incremented on each link Bit Clock period and rolls over
from FFFF_FFFFh to 0000_0000h. This counter will roll over to zero with a
period of approximately 179 seconds.
This counter is enabled while the Bit Clock bit is set to 1. Software uses
this counter to synchronize between multiple controllers. Will be reset on
controller reset.