Datasheet

Intel
®
High Definition Audio
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D27:F0
Intel
®
Atom™ Processor E6xx Series Datasheet
184
9.3.2.1.45 Offset 100Ch: FIFOTRK – FIFO Tracking Register
9.3.2.1.46 Offset 1010h, 1014h, 1020h, 1024h: I0DPIB, I1DPIB, O0DPIB, O1DPIB –
Input/Output Stream Descriptor [0-1] DMA Position in Buffer Register
Table 270. 100Ch: FIFOTRK – FIFO Tracking Register
Size: 32 bit Default: 000F_F800h Power Well: Core
Access
PCI Configuration B:D:F 0:27:0
Offset Start:
Offset End:
100Ch
100Fh
Memory Mapped IO BAR: Offset:
Bit Range Default Access Acronym Description
31 :20 0 RO RSVD Reserved
19 :11 1FFh RO MSTS
Minimum Status: Tracks the minimum FIFO free count for inbound
engines, and the minimum avail count for outbound engines when the EN
is set and the R is de-asserted. The FIFO of the DMA selected by the
DMASEL will be tracked.
10 :05 0h RO EC
Error Count; Increment each time a FIFO error occurs in the FIFO which
the DMA select is pointing to when the enable bit is set and R is de-
asserted. When the EC reaches the max count of 1FFh (63), the count
saturates and hold the max count until it is reset.
04 :02 0h RW SEL
Select: The MSTS and EC track the FIFO for the DMA select by this
register. The mapping is as follows:
000: Output DMA 0
001: Output DMA 1
010: Reserved
011: Reserved
100: Input DMA 0
101: Input DMA 1
110: Reserved
111: Reserved
01 0 RW EN
Enable: When set to 1, the MSTS and the EC fields in this register track
the minimum FIFO status or error count. When set to 0, the MSTS and
the EC fields hold its previous value.
00 0 RW R
Reset: When set to 1, the MSTS and the EC are reset to their default
value.
Table 271. 1010h, 1014h, 1020h, 1024h: I0DPIB, I1DPIB, O0DPIB, O1DPIB –
Input/Output Stream Descriptor [0-1] DMA Position in Buffer Register
Size: 32 bit Default: 0000_0000h Power Well: Core
Access
PCI Configuration B:D:F 0:27:0
Offset Start:
Offset End:
1010h, 1014h, 1020h,
1024h
1013h, 1017h, 1023h,
1027h
Memory Mapped IO BAR: Offset:
Bit Range Default Access Acronym Description
31 :00 00h RO POS
Position: Indicates the number of bytes “processed” by the DMA engine
from the beginning of the BDL. For output streams, it is incremented
when data is loaded into the FIFO.