Datasheet

Intel
®
High Definition Audio
β
D27:F0
Intel
®
Atom™ Processor E6xx Series Datasheet
182
9.3.2.1.42 Offset 1000h: EM1 – Extended Mode 1 Register
06 :01 0 RO RSVD Reserved
00 0 RW/WO PROT
Protect: When this bit is set to 1, bits [31:7, 0] of this register are Write
Only and will return 0 when read. When this bit is cleared to 0, bits
[31:7, 0] are RW. Tis bit can only be changed when all four bytes of this
register are written in a single write operation. If less than four bytes are
written this bit retains its previous value.
Table 267. 1000h: EM1 – Extended Mode 1 Register (Sheet 1 of 2)
Size: 32 bit Default: 0000_0000h Power Well: Core
Access
PCI Configuration B:D:F 0:27:0
Offset Start:
Offset End:
1000h
1003h
Memory Mapped IO BAR: Offset:
Bit Range Default Access Acronym Description
31 :24 0 RO RSVD Reserved
28 0 RW LPBKEN
Loopback Enable: When set, output data is rerouted to the input. Each
input has its own loopback enable.
27 :26 0 RW FREECNTREQ
Free Count Request: This field determines the clock in which freecnt
will be requested from the XFR layer. BIOS or software must set
FREECNTREQ to “11”
Any other selection will cause RIRB failures.
25 0 RW PSEL
Phase Select: Sets the input data sample point within phyclk.
1 = Phase C,
0 = Phase D
24 1 RW 128_4K
Boundary Break: Sets the break boundary for reads.
0 = 4KB
1 = 128B
23 :21 000 RW CORBPACE
CORB Pace: Determines the rate at which CORB commands are issued
on the link.
000 = Every Frame
001 = Every 2 Frames
......
111 = Every 8 Frames
20 0 RW FRS
FIFO Ready Select: When cleared, SDS.FRDY is asserted when there
are 2 or more packets available in the FIFO. When set, SDS.FRDY is
asserted when there are one or more packets available in the FIFO.
19 :15 0 RO RSVD Reserved
14 0 RW 48k_EN
48 KHz Enable: When set, the processor adds one extra bitclk to every
twelfth frame. When cleared, it will use the normal functionality and send
500 bitclks per frame.
13 0 RW DETS
Dock Enable Signal Transition Select: When set, HDA_DOCK_EN_B
transitions off the falling edge of BCLK (phase C). When cleared,
HDA_DOCK_EN_B transitions 1/4 BCLK after the falling edge of BCLK
(phase D).
Table 266. 98h, B8h, D8h, F8h: ISD0BDPL, ISD1BDPL, OSD0BDPL, OSD1BDPL –
Input/Output Stream Descriptor [0-1] Buffer Descriptor List Pointer Register
(Sheet 2 of 2)
Size: 32 bit Default: 0000_0000h Power Well: Core
Access
PCI Configuration B:D:F 0:27:0
Offset Start:
Offset End:
98h, B8h, D8h, F8h
9Bh, BBh, DBh, FBh
Memory Mapped IO BAR: LBAR Offset:
Bit Range Default Access Acronym Description