Datasheet
Intel
®
High Definition Audio
β
D27:F0
Intel
®
Atom™ Processor E6xx Series Datasheet
181
9.3.2.1.41 Offset 98h, B8h, D8h, F8h: ISD0BDPL, ISD1BDPL, OSD0BDPL, OSD1BDPL –
Input/Output Stream Descriptor [0-1] Buffer Descriptor List Pointer Register
13 :11 000b RW MULT
Sample Base Rate Multiple:
000=48 kHz/44.1 kHz or less
001=x2 (96 kHz, 88.2 kHz, 32 kHz)
010=x3 (144 kHz)
011=x4 (192 kHz, 176.4 kHz)
100-111=Reserved
10 :08 000b RW DIV
Sample Base Rate Divisor:
000=Divide by 1 (48 kHz, 44.1 kHz)
001=Divide by 2 (24 kHz, 22.05 kHz)
010=Divide by 3 (16 kHz, 32 kHz)
011=Divide by 4 (11.025 kHz)
100=Divide by 5 (9.6 kHz)
101=Divide by 6 (8 kHz)
110=Divide by 7
111=Divide by 8 (6 kHz)
07 0 RO RSVD Reserved
06 :04 000b RW BITS
Bits per Sample:
000=8 bits. The data will be packed in memory in 8-bit containers on 16-
bit boundaries
001=16 bits. The data will be packed in memory in 16-bit containers on
16-bit boundaries
010=20 bits. The data will be packed in memory in 32-bit containers on
32- bit boundaries
011=24 bits. The data will be packed in memory in 32-bit containers on
32- bit boundaries
100=32 bits. The data will be packed in memory in 32-bit containers on
32- bit boundaries
Others =Reserved
03 :00 0000 RW CHAN
Number of Channels: Number of channels in each frame of the stream:
0000=1
0001=2
…
1111=16
Table 266. 98h, B8h, D8h, F8h: ISD0BDPL, ISD1BDPL, OSD0BDPL, OSD1BDPL –
Input/Output Stream Descriptor [0-1] Buffer Descriptor List Pointer Register
(Sheet 1 of 2)
Size: 32 bit Default: 0000_0000h Power Well: Core
Access
PCI Configuration B:D:F 0:27:0
Offset Start:
Offset End:
98h, B8h, D8h, F8h
9Bh, BBh, DBh, FBh
Memory Mapped IO BAR: LBAR Offset:
Bit Range Default Access Acronym Description
31 :07 0 RW BDLBASE
Buffer Descriptor List Base Address: Lower address of the Buffer
Descriptor List. This value should only be modified when the RUN bit is ‘0’
or DMA transfers may be corrupted.
Table 265. 92h, B2h, D2h, F2h: ISD0FMT, ISD1FMT, OSD0FMT, OSD1FMT – Input/Output
Stream Descriptor [0-1] Format Register (Sheet 2 of 2)
Size: 16 bit Default: 0000h Power Well: Core
Access
PCI Configuration B:D:F 0:27:0
Offset Start:
Offset End:
92h, B2h, D2h, F2h
93h, B3h, D3h, F3h
Memory Mapped IO BAR: LBAR Offset:
Bit Range Default Access Acronym Description