Datasheet

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Intel

Atom™ Processor E6xx Series Datasheet

266 98h, B8h, D8h, F8h: ISD0BDPL, ISD1BDPL, OSD0BDPL, OSD1BDPL – Input/Output

Stream Descriptor [0-1] Buffer Descriptor List Pointer Register.....................................181

267 1000h: EM1 – Extended Mode 1 Register...................................................................182

268 1004h: INRC – Input Stream Repeat Count Register ...................................................183

269 1008h: OUTRC – Output Stream Repeat Count Register...............................................183

270 100Ch: FIFOTRK – FIFO Tracking Register .................................................................184

271 1010h, 1014h, 1020h, 1024h: I0DPIB, I1DPIB, O0DPIB, O1DPIB – Input/Output Stream

Descriptor [0-1] DMA Position in Buffer Register.........................................................184

272 1030h: EM2 – Extended Mode 2 Register...................................................................185

273 2030h: WLCLKA – Wall Clock Alias Register ...............................................................185

274 2084h, 20A4h, 2104h, 2124h: ISD0LPIBA, ISD1LPIBA, OSD0LPIBA, OSD1LPIBA – Input/

Output Stream Descriptor [0-1] Link Position in Buffer Alias Register.............................186

275 LPC Interface PCI Register Address Map ....................................................................188

276 Offset 00h: ID – Identifiers......................................................................................188

277 Offset 04h: CMD – Device Command.........................................................................189

278 Offset 06h: STS – Device Status...............................................................................189

279 Offset 08h: RID – Revision ID ..................................................................................189

280 Offset 09h: CC – Class Code ....................................................................................190

281 Offset 0Eh: HDTYPE – Header Type...........................................................................190

282 Offset 2Ch: SS – Subsystem Identifiers.....................................................................190

283 Offset 40h: SMBA – SMBus Base Address ..................................................................191

284 Offset 44h: GBA – GPIO Base Address.......................................................................191

285 Offset 48h: PM1BLK – PM1_BLK Base Address............................................................191

286 Offset 4Ch: GPE0BLK – GPE0_BLK Base Address.........................................................192

287 Offset 54h: LPCS – LPC Clock Strength Control...........................................................192

288 Offset 58h: ACTL – ACPI Control...............................................................................193

289 Offset 5Ch: MC – Miscellaneous Control.....................................................................193

290 Offset 60h – 67h: PxRC – PIRQ[A-H] Routing Control..................................................195

291 Offset 68h: SCNT – Serial IRQ Control.......................................................................196

292 Offset 84h: WDTBA – WDT Base Address...................................................................196

293 Offset D0h: FS – FWH ID Select ...............................................................................196

294 Offset D4h: BDE – BIOS Decode Enable.....................................................................197

295 Offset D8h: BC – BIOS Control.................................................................................198

296 Offset F0h: RCBA – Root Complex Base Address.........................................................199

297 Timer I/O Registers ................................................................................................201

298 43h: TCW - Timer Control Word Register ...................................................................202

299 43h: RBC – Read Back Command .............................................................................203

300 43h: CLC – Counter Latch Command.........................................................................203

301 40h, 41h, 42h: Interval Timer Status Byte Format Register..........................................204

302 40h, 41h, 42h: Counter Access Ports Register ............................................................204

303 HPET Registers.......................................................................................................206

304 000h: GCID – General Capabilities and ID .................................................................207

305 010h: GC – General Configuration ............................................................................207

306 020h: GIS – General Interrupt Status .......................................................................208

307 0F0h: MCV – Main Counter Value..............................................................................208

308 100h, 120h, 140h: T[0-2]C – Timer [0-2] Config and Capabilities .................................208

309 108h, 128h, 148h: T[0-2]CV – Timer [0-2] Comparator Value......................................210

310 Timer Interrupt Mapping: Legacy Option....................................................................211

311 Master 8259 Input Mapping .....................................................................................212

312 Slave 8259 Input Mapping .......................................................................................212

313 8259 I/O Register Mapping .....................................................................................213

314 20h, A0h: ICW1 – Initialization Command Word 1.......................................................213

315 21h, A1h: ICW2 – Initialization Command Word 2.......................................................214

316 21h: MICW3 – Master Initialization Command Word 3 .................................................215

317 A1h: SICW3 – Slave Initialization Command Word 3 ...................................................215