Datasheet
Intel
®
High Definition Audio
β
D27:F0
Intel
®
Atom™ Processor E6xx Series Datasheet
179
9.3.2.1.38
,
Offset 90h, B0h: ISD0FIFOS, ISD1FIFOS – Input Stream Descriptor [0-1] FIFO
Size Register
9.3.2.1.39 Offset D0h, F0h: OSD0FIFOS, OSD1FIFOS – Output Stream Descriptor [0-1]
FIFO Size Register
Table 263. 90h, B0h: ISD0FIFOS, ISD1FIFOS – Input Stream Descriptor [0-1] FIFO Size
Register
Size: 16 bit Default: 0077h Power Well: Core
Access
PCI Configuration B:D:F 0:27:0
Offset Start:
Offset End:
90h, B0h
91h, B1h
Memory Mapped IO BAR: LBAR Offset:
Bit Range Default Access Acronym Description
15 :08 0 RO RSVD Reserved
07 :00 77h RO FIFOS
FIFO Size: Indicates the maximum number of bytes that could be
fetched by the controller at one time. This is the maximum number of
bytes that may have been DMA’d into memory but not yet transmitted on
the link, and is also the maximum possible value that the PICB count will
increase by at one time.
The value in this field is different for input and output streams. It is also
dependent on the Bits per Sample setting for the corresponding stream.
Following table shows the values read/written from/to this register for
input and output streams, and for non-padded and padded bit formats:
For Output Stream, FIFOS is a RW field. The default after reset is BFh:
Notes:
1. All other values are Not Supported.
2. When the output stream is programmed to an unsupported size,
the hardware sets itself to the default value (BFh)
3. Software must read the bit field to test if the value is supported
after setting the bit field.
For Input Stream, FIFOS is a RO field with the following value:
8, 16, 32-bit Input Streams: 120B = 77h
20, 24-bit Input Streams: 160B = 9Fh
Note the default value is different for input and output streams, and
reflects the default state of the BITS fields (in Stream Descriptor Format
registers) for the corresponding stream.
Table 264. D0h, F0h: OSD0FIFOS, OSD1FIFOS – Output Stream Descriptor [0-1] FIFO
Size Register (Sheet 1 of 2)
Size: 16 bit Default: 00BFh Power Well: Core
Access
PCI Configuration B:D:F 0:27:0
Offset Start:
Offset End:
D0h, F0h
D1h, F1h
Memory Mapped IO BAR: LBAR Offset:
Bit Range Default Access Acronym Description
15 :08 0 RO RSVD Reserved
Value
1
Output Streams
0Fh = 16B 8, 16, 20, 24 or 32 bit Output Streams
1Fh = 32B 8, 16, 20, 24 or 32 bit Output Streams
3Fh = 64B 8, 16, 20, 24 or 32 bit Output Streams
7Fh = 128B 8, 16, 20, 24 or 32 bit Output Streams
BFh = 192B 8, 16 or 32 bit Output Streams
FFh = 256B 20, 24 bit Output Streams