Datasheet

Intel
®
High Definition Audio
β
D27:F0
Intel
®
Atom™ Processor E6xx Series Datasheet
178
9.3.2.1.37 Offset 8Eh, AEh, CEh, EEh: ISD0FIFOW, ISD1FIFOW, OSD0FIFOW,
OSD1FIFOW– Input/Output Stream Descriptor [0-1] FIFO Watermark
Register
07 :00 00h RW LVI
Last Valid Index: The value written to this register indicates the index
for the last valid Buffer Descriptor in the BDL. After the controller has
processed this descriptor, it will wrap back to the first descriptor in the list
and continue processing.
LVI must be at least 1; i.e., there must be at least two valid entries in the
buffer descriptor list before DMA operations can begin.
This value should only be modified when the RUN bit is ‘0’
Table 262. 8Eh, AEh, CEh, EEh: ISD0FIFOW, ISD1FIFOW, OSD0FIFOW, OSD1FIFOW–
Input/Output Stream Descriptor [0-1] FIFO Watermark Register
Size: 16 bit Default: 0004h Power Well: Core
Access
PCI Configuration B:D:F 0:27:0
Offset Start:
Offset End:
8Eh, AEh, CEh, EEh
8Fh, AFh, CFh, EFh
Memory Mapped IO BAR: LBAR Offset:
Bit Range Default Access Acronym Description
15 :03 0 RO RSVD Reserved
02 :00 100b RW FIFOW
FIFO Watermark: Indicates the minimum number of bytes
accumulated/free in the FIFO before the controller will start a
fetch/eviction of data.
010 8B Supported
011 16B Supported
100 32B Supported (Default)
other Unsupported
Note: When the bit field is programmed to an unsupported size, the
hardware sets itself to the default value.
Software must read the bit field to test if the value is supported after
setting the bit field.
Table 261. 8Ch, ACh, CCh, ECh: ISD0LVI, ISD1LVI, OSD0LVI, OSD1LVI– Input/Output
Stream Descriptor [0-1] Last Valid Index Register (Sheet 2 of 2)
Size: 16 bit Default: 0000h Power Well: Core
Access
PCI Configuration B:D:F 0:27:0
Offset Start:
Offset End:
8Ch, ACh
CCh, ECh
8Dh, ADh
CDh, EDh
Memory Mapped IO BAR: LBAR Offset:
Bit Range Default Access Acronym Description