Datasheet
Intel
®
High Definition Audio
β
D27:F0
Intel
®
Atom™ Processor E6xx Series Datasheet
177
9.3.2.1.34 Offset 84h, A4h, C4h, E4h: ISD0LPIB, ISD1LPIB, OSD0LPIB, OSD1LPIB –
Input/Output Stream Descriptor [0-1] Link Position in Buffer Register
9.3.2.1.35 Offset 88h, A8h, C8h, E8h: ISD0CBL, ISD1CBL, OSD0CBL, OSD1CBL–
Input/Output Stream Descriptor [0-1] Cyclic Buffer Length Register
9.3.2.1.36 Offset 8Ch, ACh, CCh, ECh: ISD0LVI, ISD1LVI, OSD0LVI, OSD1LVI–
Input/Output Stream Descriptor [0-1] Last Valid Index Register
Table 259. 84h, A4h, C4h, E4h: ISD0LPIB, ISD1LPIB, OSD0LPIB, OSD1LPIB –
Input/Output Stream Descriptor [0-1] Link Position in Buffer Register
Size: 32 bit Default: 0000_0000h Power Well: Core
Access
PCI Configuration B:D:F 0:27:0
Offset Start:
Offset End:
84h, A4h, C4h,E4h
87h, A7h, C7h, E7h
Memory Mapped IO BAR: LBAR Offset:
Bit Range Default Access Acronym Description
31 :00 0 RO LPIB
Link Position in Buffer: Indicates the number of bytes that have been
received off the link. This register will count from 0 to the value in the
Cyclic Buffer Length register and then wrap to 0.
Table 260. 88h, A8h, C8h, E8h: ISD0CBL, ISD1CBL, OSD0CBL, OSD1CBL– Input/Output
Stream Descriptor [0-1] Cyclic Buffer Length Register
Size: 32 bit Default: 0000_0000h Power Well: Core
Access
PCI Configuration B:D:F 0:27:0
Offset Start:
Offset End:
88h, A8h, C8h, E8h
8Bh, ABh, CBh, EBh
Memory Mapped IO BAR: LBAR Offset:
Bit Range Default Access Acronym Description
31 :00 0 RW CBL
Length: Indicates the number of bytes in the complete cyclic buffer. CBL
must represent an integer number of samples. Link Position in Buffer
(LPIB) will be reset when it reaches this value.
Software may only write to this register after Global Reset, Controller
Reset, or Stream Reset has occurred. This value should only be modified
when the RUN bit is ‘0’. Once the RUN bit has been set to enable the
engine, software must not write to this register until after the next reset
is asserted, or transfers may be corrupted.
Table 261. 8Ch, ACh, CCh, ECh: ISD0LVI, ISD1LVI, OSD0LVI, OSD1LVI– Input/Output
Stream Descriptor [0-1] Last Valid Index Register (Sheet 1 of 2)
Size: 16 bit Default: 0000h Power Well: Core
Access
PCI Configuration B:D:F 0:27:0
Offset Start:
Offset End:
8Ch, ACh
CCh, ECh
8Dh, ADh
CDh, EDh
Memory Mapped IO BAR: LBAR Offset:
Bit Range Default Access Acronym Description
15 :08 0 RO RSVD Reserved