Datasheet

Intel
®
High Definition Audio
β
D27:F0
Intel
®
Atom™ Processor E6xx Series Datasheet
176
9.3.2.1.33 Offset 83h, A3h, C3h, E3h: ISD0STS, ISD1STS, OSD0STS, OSD1STS –
Input/Output Stream Descriptor [0-1] Status Register
00 0 RW SRST
Stream Reset:
0 = Writing a 0 causes the corresponding stream to exit reset. When the
stream hardware is ready to begin operation, it will report a 0 in this bit.
Software must read a 0 from this bit before accessing any of the stream
registers.
1 = Writing a 1 causes the corresponding stream to be reset. The Stream
Descriptor registers (except the SRST bit itself) and FIFO’s for the
corresponding stream are reset. After the stream hardware has
completed sequencing into the reset state, it will report a 1 in this bit.
Software must read a 1 from this bit to verify that the stream is in reset.
The RUN bit must be cleared before SRST is asserted.
Table 258. 83h, A3h, C3h, E3h: ISD0STS, ISD1STS, OSD0STS, OSD1STS – Input/Output
Stream Descriptor [0-1] Status Register
Size: 8 bit Default: 00h Power Well: Core
Access
PCI Configuration B:D:F 0:27:0
Offset Start:
Offset End:
83h, A3h, C3h, E3h
83h, A3h, C3h, E3h
Memory Mapped IO BAR: LBAR Offset:
Bit Range Default Access Acronym Description
07 :06 0 RW RO Reserved
05 0 RO RO
FIFO Ready: For output streams, the Intel
®
High Definition Audio
β
controller hardware will set this bit to a 1 while the output DMA FIFO
contains enough data to maintain the stream on then link. This bit
defaults to 0 on reset because the FIFO is cleared on a reset.
For input streams, the Intel
®
High Definition Audio
β
controller hardware
will set this bit to 1 when a valid descriptor is loaded and the engine is
ready for the RUN bit to be set.
04 0 RO RWC
Descriptor Error: When set, this bit Indicates that a serious error
occurred during the fetch of a descriptor. This could be a result of a
Master Abort, a Parity or ECC error on the bus, or any other error which
renders the current Buffer Descriptor or Buffer Descriptor List useless.
This error is treated as a fatal stream error, as the stream cannot
continue running. The RUN bit will be cleared and the stream will stop.
Software may attempt to restart the stream engine after addressing the
cause of the error and writing a ‘1’ to this bit to clear it.
03 0 RO RWC
FIFO Error: This bit is set when a FIFO error occurs. This bit is set even
if an interrupt is not enabled.
For an input stream, this indicates a FIFO overrun occurring while the
RUN bit is set. When this happens, the FIFO pointers don’t increment and
the incoming data is not written into the FIFO, thereby being lost.
For an output stream, this indicates a FIFO under run when there are still
buffers to send. The hardware should not transmit anything on the link
for the associated stream if there is not valid data to send.
02 0 RO RWC
Buffer Completion Interrupt Status: This bit is set to 1 by the
hardware after the last sample of a buffer has been processed, AND if the
Interrupt on Completion (IOC) bit is set in the command byte of the
buffer descriptor. It remains active until software clears it by writing a 1
to this bit position.
01 :00 0 RW RO Reserved
Table 257. 80h, A0h, C0h, E0h: ISD0CTL, ISD1CTL, OSD0CTL, OSD1CTL – Input/Output
Stream Descriptor [0-1] Control Register (Sheet 2 of 2)
Size: 24 bit Default: 04_0000h Power Well: Core
Access
PCI Configuration B:D:F 0:27:0
Offset Start:
Offset End:
80h, A0h, C0h, E0h
82h, A2h, C2h, E2h
Memory Mapped IO BAR: LBAR Offset:
Bit Range Default Access Acronym Description