Datasheet

Intel
®
High Definition Audio
β
D27:F0
Intel
®
Atom™ Processor E6xx Series Datasheet
175
9.3.2.1.32 Offset 80h, A0h, C0h, E0h: ISD0CTL, ISD1CTL, OSD0CTL, OSD1CTL –
Input/Output Stream Descriptor [0-1] Control Register
Table 257. 80h, A0h, C0h, E0h: ISD0CTL, ISD1CTL, OSD0CTL, OSD1CTL – Input/Output
Stream Descriptor [0-1] Control Register (Sheet 1 of 2)
Size: 24 bit Default: 04_0000h Power Well: Core
Access
PCI Configuration B:D:F 0:27:0
Offset Start:
Offset End:
80h, A0h, C0h, E0h
82h, A2h, C2h, E2h
Memory Mapped IO BAR: LBAR Offset:
Bit Range Default Access Acronym Description
23 :20 0 RW STRM
Stream Number: This value reflects the Tag associated with the data
being transferred on the link.
When data controlled by this descriptor is sent out over the link, it will
have this stream number encoded on the HDA_SYNC signal.
When an input stream is detected on any of the HDA_SDI[x] signals that
match this value, the data samples are loaded into the FIFO associated
with this descriptor.
Note that while a single HDA_SDI[x] input may contain data from more
than one stream number, two different HDA_SDI[x] inputs may not be
configured with the same stream number.
0000=Reserved (Indicates Unused)
0001=Stream 1
…
1110=Stream 14
1111=Stream 15
19 0 RO DIR
Bidirectional Direction Control: This bit is only meaningful for
Bidirectional streams. Therefore this bit is hardwired to 0.
18 1 RO TP
Traffic Priority: Hardwired to 1 indicating that all streams will use VC1 if
it is enabled throughout the PCI Express* registers.
17 :16 00 RO STRIPE
Stripe Control: This field is meaningless for input streams. Therefore it
is hardwired to 0’s.
15 :05 0 RO RSVD Reserved
04 0 RW DEIE
Descriptor Error Interrupt Enable:
0 = Disable
1 = An interrupt is generated when the Descriptor Error Status (DESE)
bit is set.
03 0 RW FEIE
FIFO Error Interrupt Enable: This bit controls whether the occurrence
of a FIFO error (overrun for input or underrun for output) will cause an
interrupt or not. If this bit is not set, bit 3 in the Status register will be
set, but the interrupt will not occur. Either way, the samples will be
dropped.
02 0 RW IOCE
Interrupt On Completion Enable: This bit controls whether or not an
interrupt occurs when a buffer completes with the IOC bit set in its
descriptor. If this bit is not set, bit 2 in the Status register will be set, but
the interrupt will not occur
01 0 RW RUN
Stream Run:
0 = The DMA engine associated with this input stream will be disabled.
Hardware will report a 0 in this bit when the DMA engine is actually
stopped. Software must read a 0 from this bit before modifying related
control registers or restarting the DMA engine.
1 = The DMA engine associated with this input stream will be enabled to
transfer data from the FIFO to main memory. The SSYNC bit must also be
cleared in order for the DMA engine to run. For output streams, the
cadence generator is reset whenever the RUN bit is set.