Datasheet
Intel
®
High Definition Audio
β
D27:F0
Intel
®
Atom™ Processor E6xx Series Datasheet
174
9.3.2.1.31 Offset 70h: DPBASE – DMA Position Base Address Register
00 0 RW ICB
Immediate Command Busy: When this bit as read as a 0 it indicates
that a new command may be issued using the Immediate Command
mechanism. When this bit transitions from a 0 to a 1 (via software
writing a 1), the controller issues the command currently stored in the
Immediate Command register to the codec over the link. When the
corresponding response is latched into the Immediate Response register,
the controller hardware sets the IRV flag and clears the ICB bit back to 0.
Note that an Immediate Command must not be issued while the
CORB/RIRB mechanism is operating, otherwise the responses conflict.
This must be enforced by software.
Table 256. 70h: DPBASE – DMA Position Base Address Register
Size: 32 bit Default: 0000_0000h Power Well: Core
Access
PCI Configuration B:D:F 0:27:0
Offset Start:
Offset End:
70h
73h
Memory Mapped IO BAR: LBAR Offset:
Bit Range Default Access Acronym Description
31 :07 0 RW DPBASE
DMA Position Base Address: This field is the 32 bits of the DMA
Position Buffer Base Address. This register field must not be written when
any DMA engine is running or the DMA transfer may be corrupted. This
same address is used by the Flush Control, and must be programmed
with a valid value before the FLCNRTL bit (LBAR + 08h: bit 1) is set.
06 :01 0 RO RSVD Reserved
00 0 RW
DMA Position Buffer Enable: When this bit is set to a ‘1’, the controller
will write the DMA positions of each of the DMA engines to the buffer in
main memory periodically (typically once/frame). Software can use this
value to know what data in memory is valid data.
Table 255. 68h: ICS – Immediate Command Status (Sheet 2 of 2)
Size: 16 bit Default: 0000h Power Well: Core
Access
PCI Configuration B:D:F 0:27:0
Offset Start:
Offset End:
68h
69h
Memory Mapped IO BAR: LBAR Offset:
Bit Range Default Access Acronym Description