Datasheet
Intel
®
High Definition Audio
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D27:F0
Intel
®
Atom™ Processor E6xx Series Datasheet
172
9.3.2.1.26 Offset 5Dh: RIRBSTS - RIRB Status Register
9.3.2.1.27 Offset 5Eh: RIRBSIZE - RIRB Size Register
Table 251. 5Dh: RIRBSTS - RIRB Status Register
Size: 8 bit Default: 00h Power Well: Core
Access
PCI Configuration B:D:F 0:27:0
Offset Start:
Offset End:
5Dh
5Dh
Memory Mapped IO BAR: LBAR Offset:
Bit Range Default Access Acronym Description
07 :03 0 RO RSVD Reserved
02 0 RWC RIRBOIS
Response Overrun Interrupt Status: Hardware sets this bit to a 1
when the RIRB DMA engine is not able to write the incoming responses to
memory before additional incoming responses overrun the internal FIFO.
When the overrun occurs, the hardware will drop the responses which
overrun the buffer. An interrupt may be generated if the Response
Overrun Interrupt Control bit is set. Note that this status bit is set even if
an interrupt is not enabled for this event. Software clears this flag by
writing a 1 to this bit.
01 0 RO RSVD Reserved
00 0 RWC RINTFL
Response Interrupt: Hardware sets this bit to a 1 when an interrupt
has been generated after N number of Responses are sent to the RIRB
buffer OR when an empty Response slot is encountered on all
HDA_SDI[x] inputs (whichever occurs first). Note that this status bit is
set even if an interrupt is not enabled for this event. Software clears this
flag by writing a 1 to this bit.
Table 252. 5Eh: RIRBSIZE - RIRB Size Register
Size: 8 bit Default: 42h Power Well: Core
Access
PCI Configuration B:D:F 0:27:0
Offset Start:
Offset End:
5Eh
5Eh
Memory Mapped IO BAR: LBAR Offset:
Bit Range Default Access Acronym Description
07 :04 0100b RO RIRBSZCAP
RIRB Size Capability: 0100b indicates that the processor only supports
a RIRB size of 256 RIRB entries (2048B).
03 :02 0 RO RSVD Reserved
01 :00 10 RO RIRBSIZE
RIRB Size: Hardwired to 10b which sets the RIRB size to 256 entries
(2048B).