Datasheet
Intel
®
High Definition Audio
β
D27:F0
Intel
®
Atom™ Processor E6xx Series Datasheet
171
9.3.2.1.24 Offset 5Ah: RINTCNT – Response Interrupt Count Register
9.3.2.1.25 Offset 5Ch: RIRBCTL - RIRB Control Register
Table 249. 5Ah: RINTCNT – Response Interrupt Count Register
Size: 16 bit Default: 0000h Power Well: Core
Access
PCI Configuration B:D:F 0:27:0
Offset Start:
Offset End:
5Ah
5Bh
Memory Mapped IO BAR: LBAR Offset:
Bit Range Default Access Acronym Description
15 :08 0 RO RSVD Reserved
07 :00 00h RW RINTCNT
N Response Interrupt Count:
0000_0001b = 1 Response sent to RIRB
…
1111_1111b = 255 Responses sent to RIRB
0000_0000b = 256 Responses sent to RIRB
The DMA engine should be stopped when changing this field or else an
interrupt may be lost.
Note that each Response occupies 2 Dwords in the RIRB.
This is compared to the total number of responses that have been
returned, as opposed to the number of frames in which there were
responses. If more than one codec responds in one frame, then the count
is increased by the number of responses received in the frame.
Table 250. 5Ch: RIRBCTL - RIRB Control Register
Size: 8 bit Default: 00h Power Well: Core
Access
PCI Configuration B:D:F 0:27:0
Offset Start:
Offset End:
5Ch
5Ch
Memory Mapped IO BAR: LBAR Offset:
Bit Range Default Access Acronym Description
07 :03 0 RO RSVD Reserved
02 0 RW RIRBOIC
Response Overrun Interrupt Control: If this bit is set, the hardware
will generate an interrupt when the Response Overrun Interrupt Status
bit (LBAR + 5Dh: bit 2) is set.
01 0 RW RIRBRUN
Enable RIRB DMA Engine:
0 = DMA Stop
1 = DMA Run
After software writes a 0 to this bit, the hardware may not stop
immediately. The hardware will physically update the bit to a 0 when the
DMA engine is truly stopped. Software must read a 0 from this bit to
verify that the DMA is truly stopped.
00 0 RW RINTCTL
Response Interrupt Control:
0 = Disable Interrupt
1 = Generate an interrupt after N number of Responses are sent to the
RIRB buffer OR when an empty Response slot is encountered on all
HDA_SDI[x] inputs (whichever occurs first). The N counter is reset when
the interrupt is generated.