Datasheet

Intel
®
High Definition Audio
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D27:F0
Intel
®
Atom™ Processor E6xx Series Datasheet
170
9.3.2.1.21 Offset 4Eh: CORBSIZE - CORB Size Register
9.3.2.1.22 Offset 50h: RIRBBASE - RIRB Base Address Register
9.3.2.1.23 Offset 58h: RIRBWP - RIRB Write Pointer Register
Table 246. 4Eh: CORBSIZE - CORB Size Register
Size: 8 bit Default: 42h Power Well: Core
Access
PCI Configuration B:D:F 0:27:0
Offset Start:
Offset End:
4Eh
4Eh
Memory Mapped IO BAR: LBAR Offset:
Bit Range Default Access Acronym Description
07 :04 0100b RO CORBSZCAP
CORB Size Capability: 0100b indicates that the processor only supports
a CORB size of 256 CORB entries (1024B).
03 :02 0 RO RSVD Reserved
01 :00 10b RO CORBSIZE
CORB Size: Hardwired to 10b which sets the CORB size to 256 entries
(1024B).
Table 247. 50h: RIRBBASE - RIRB Base Address Register
Size: 32 bit Default: 0000_0000h Power Well: Core
Access
PCI Configuration B:D:F 0:27:0
Offset Start:
Offset End:
50h
53h
Memory Mapped IO BAR: LBAR Offset:
Bit Range Default Access Acronym Description
31 :07 0 RW RIRBBASE
RIRB Base Address: This field is the address of the Response Input
Ring Buffer, allowing the RIRB Base Address to be assigned on any 128-B
boundary. This register field must not be written when the DMA engine is
running or the DMA transfer may be corrupted.
06 :00 0 RO RSVD Reserved
Table 248. 58h: RIRBWP - RIRB Write Pointer Register
Size: 16 bit Default: 0000h Power Well: Core
Access
PCI Configuration B:D:F 0:27:0
Offset Start:
Offset End:
58h
59h
Memory Mapped IO BAR: LBAR Offset:
Bit Range Default Access Acronym Description
15 0 WO RIRBWPRST
RIRB Write Pointer Reset: Software writes a 1 to this bit to reset the
RIRB Write Pointer to 0. The RIRB DMA engine must be stopped prior to
resetting the Write Pointer or else DMA transfer may be corrupted. This
bit will always be read as 0.
14 :08 0 RO RSVD Reserved
07 :00 0 RO RIRBWP
RIRB Write Pointer: Indicates the last valid RIRB entry written by the
DMA controller. Software reads this field to determine how many
responses it can read from the RIRB. The value read indicates the RIRB
Write Pointer offset in 2 Dword RIRB entry units (since each RIRB entry is
2 Dwords long). Supports up to 256 RIRB entries (256 x 8B=2KB). This
field may be read while the DMA engine is running.