Datasheet

Intel
®
High Definition Audio
β
D27:F0
Intel
®
Atom™ Processor E6xx Series Datasheet
169
9.3.2.1.19 Offset 4Ch: CORBCTL - CORB Control Register
9.3.2.1.20 Offset 4Dh: CORBSTS - CORB Status Register
07 :00 0 RO
CORB Read Pointer: Software reads this field to determine how many
commands it can write to the CORB without over-running. The value read
indicates the CORB Read Pointer offset in Dword granularity. The offset
entry read from this field has been successfully fetched by the DMA
controller and may be over-written by software. Supports 256 CORB
entries (256 x 4B=1KB). This field may be read while the DMA engine is
running.
Table 244. 4Ch: CORBCTL - CORB Control Register
Size: 8 bit Default: 0000h Power Well: Core
Access
PCI Configuration B:D:F 0:27:0
Offset Start:
Offset End:
4Ch
4Ch
Memory Mapped IO BAR: LBAR Offset:
Bit Range Default Access Acronym Description
07 :02 0 RO RSVD Reserved
01 0 RW CORBRUN
Enable CORB DMA Engine:
0 = DMA Stop
1 = DMA Run
After software writes a 0 to this bit, the hardware may not stop
immediately. The hardware will physically update the bit to a 0 when the
DMA engine is truly stopped. Software must read a 0 from this bit to
verify that the DMA is truly stopped.
00 0 RW CMEIE
CORB Memory Error Interrupt Enable: If this bit is set, the controller
will generate an interrupt if the MEI status bit (LBAR + 4Dh: bit 0) is set.
Table 245. 4Dh: CORBSTS - CORB Status Register
Size: 8 bit Default: 0000h Power Well: Core
Access
PCI Configuration B:D:F 0:27:0
Offset Start:
Offset End:
4Dh
4Dh
Memory Mapped IO BAR: LBAR Offset:
Bit Range Default Access Acronym Description
07 :01 0 RO RSVD Reserved
00 0 RW CMEI
CORB Memory Error Indication: If this status bit is set, the controller
has detected an error in the pathway between the controller and
memory. This may be an ECC bit error or any other type of detectable
data error which renders the command data fetched invalid. Software can
clear this bit by writing a 1 to it. However, this type of error leaves the
audio subsystem in an unviable state and typically requires a CRST_B.
Table 243. 4Ah: CORBRP - CORB Read Pointer Register (Sheet 2 of 2)
Size: 16 bit Default: 0000h Power Well: Core
Access
PCI Configuration B:D:F 0:27:0
Offset Start:
Offset End:
4Ah
4Bh
Memory Mapped IO BAR: LBAR Offset:
Bit Range Default Access Acronym Description