Datasheet

Intel
®
High Definition Audio
β
D27:F0
Intel
®
Atom™ Processor E6xx Series Datasheet
168
9.3.2.1.16 Offset 40h: CORBBASE - CORB Base Address Register
9.3.2.1.17 Offset 48h: CORBWP - CORB Write Pointer Register
9.3.2.1.18 Offset 4Ah: CORBRP - CORB Read Pointer Register
Table 241. 40h: CORBBASE - CORB Base Address Register
Size: 32 bit Default: 0000_0000h Power Well: Core
Access
PCI Configuration B:D:F 0:27:0
Offset Start:
Offset End:
40h
43h
Memory Mapped IO BAR: LBAR Offset:
Bit Range Default Access Acronym Description
31 :07 0 RW CORBBASE
CORB Base Address: This field is the address of the Command Output
Ring Buffer, allowing the CORB Base Address to be assigned on any 128-
B boundary. This register field must not be written when the DMA engine
is running or the DMA transfer may be corrupted.
06 :00 0 RO RSVD Reserved
Table 242. 48h: CORBWP - CORB Write Pointer Register
Size: 16 bit Default: 0000h Power Well: Core
Access
PCI Configuration B:D:F 0:27:0
Offset Start:
Offset End:
48h
49h
Memory Mapped IO BAR: LBAR Offset:
Bit Range Default Access Acronym Description
15 :08 0 RO RSVD Reserved
07 :00 0 RW CORBWP
CORB Write Pointer: Software writes the last valid CORB entry offset
into this field in Dword granularity. The DMA engine fetches commands
from the CORB until the Read Pointer matches the Write Pointer.
Supports 256 CORB entries (256 x 4B=1KB). This field may be written
while the DMA engine is running.
Table 243. 4Ah: CORBRP - CORB Read Pointer Register (Sheet 1 of 2)
Size: 16 bit Default: 0000h Power Well: Core
Access
PCI Configuration B:D:F 0:27:0
Offset Start:
Offset End:
4Ah
4Bh
Memory Mapped IO BAR: LBAR Offset:
Bit Range Default Access Acronym Description
15 0 RW RSVD
CORB Read Pointer Reset: Software writes a 1 to this bit to reset the
CORB Read Pointer to 0 and clear any residual prefetched commands in
the CORB hardware buffer within the Intel
®
HD Audio
β
controller. The
hardware will physically update this bit to 1 when the CORB Pointer reset
is complete. Software must read a 1 to verify that the reset completed
correctly. Software must clear this bit back to 0 and read back the 0 to
verify that the clear completed correctly. The CORB DMA engine must be
stopped prior to resetting the Read Pointer or else DMA transfer may be
corrupted.
14 :08 0 RO CORBWP Reserved