Datasheet

Intel
®
High Definition Audio
β
D27:F0
Intel
®
Atom™ Processor E6xx Series Datasheet
167
9.3.2.1.15 Offset 38h: SSYNC –Stream Synchronization Register
Table 239. 30h: WALCLK – Wall Clock Counter Register
Size: 32 bit Default: 0000_0000h Power Well: Core
Access
PCI Configuration B:D:F 0:27:0
Offset Start:
Offset End:
30h
33h
Memory Mapped IO BAR: LBAR Offset:
Bit Range Default Access Acronym Description
31 :00
0000_
0000h
RO Counter
Wall Clock Counter:
32 bit counter that is incremented on each link Bit Clock period and rolls
over from FFFF_FFFFh to 0000_0000h. This counter will roll over to zero
with a period of approximately 179 seconds.
This counter is enabled while the Bit Clock bit is set to 1. Software uses
this counter to synchronize between multiple controllers. Will be reset on
controller reset.
Table 240. 38h: SSYNC –Stream Synchronization Register
Size: 32 bit Default: 0000_0000h Power Well: Core
Access
PCI Configuration B:D:F 0:27:0
Offset Start:
Offset End:
38h
3Bh
Memory Mapped IO BAR: LBAR Offset:
Bit Range Default Access Acronym Description
31 :04 0 RO RSVD Reserved
03 :00 0h RW SSYNC
Stream Synchronization Bits: The Stream Synchronization bits, when
set to 1, block data from being sent on or received from the link. Each bit
controls the associated Stream Descriptor; bit 0 corresponds to the first
Stream Descriptor, etc.
To synchronously start a set of DMA engines, the bits in the SSYNC
register are first set to a 1. The RUN bits for the associated Stream
Descriptors are then set to a 1 to start the DMA engines. When all
streams are ready (FIFORDY=1), the associated SSYNC bits can all be set
to 0 at the same time, and transmission or reception of bits to or from
the link will begin together at the start of the next full link frame.
To synchronously stop streams, first the bits are set in the SSYNC
register, and then the individual RUN bits in the Stream Descriptors are
cleared by software.
The streams are numbered and the SSYNC bits assigned sequentially,
based on their order in the register set.
Bit 3: Output Stream 2 (OS2)
Bit 2: Output Stream 1 (OS1)
Bit 1: Input Stream 2 (IS2)
Bit 0: Input Stream 1 (IS1)