Datasheet

Intel
®
High Definition Audio
β
D27:F0
Intel
®
Atom™ Processor E6xx Series Datasheet
166
9.3.2.1.13 Offset 24h: INTSTS - Interrupt Status Register
9.3.2.1.14 Offset 30h: WALCLK – Wall Clock Counter Register
The 32 bit monotonic counter provides a ‘wall clock’ that can be used by system
software to synchronize independent audio controllers. The counter must be
implemented.
29 :04 0 RO RSVD Reserved
03 :00 0h RW SIE
Stream Interrupt Enable: When set to 1 the individual Streams are
enabled to generate an interrupt when the corresponding stream status
(INTSTS) bits get set.
The streams are numbered and the SIE bits assigned sequentially, based
on their order in the register set.
Bit 3: Output Stream 2 (OS2)
Bit 2: Output Stream 1 (OS1)
Bit 1: Input Stream 2 (IS2)
Bit 0: Input Stream 1 (IS1)
Table 238. 24h: INTSTS - Interrupt Status Register
Size: 32 bit Default: 0000_0000h Power Well: Core
Access
PCI Configuration B:D:F 0:27:0
Offset Start:
Offset End:
24h
27h
Memory Mapped IO BAR: LBAR Offset:
Bit Range Default Access Acronym Description
31 0 RO GIS
Global Interrupt Status: This bit is an OR of all of the interrupt status
bits in this register.
Note: This bit is not affected by the D3
HOT
to D0 transition.
30 0 RO CIS
Controller Interrupt Status: Status of general controller interrupt.
1 = indicates that an interrupt condition occurred due to a Response
Interrupt, a Response Buffer Overrun Interrupt or a SDIN State Change
event. The exact cause can be determined by interrogating other
registers. This bit is an OR of all of the stated interrupt status bits for this
register.
Note:
This bit is set regardless of the state of the corresponding interrupt
enable bit, but a hardware interrupt will not be generated unless the
corresponding enable bit is set.
This bit is not affected by the D3
HOT
to D0 transition.
29 :04 0 RO RSVD Reserved
03 :00 0h RO SIS
Stream Interrupt Status: A 1 indicates that an interrupt condition
occurred on the corresponding Stream. Note that a HW interrupt will not
be generated unless the corresponding enable bit is set. This bit is an OR
of all of an individual stream’s interrupt status bits.
The streams are numbered and the SIS bits assigned sequentially, based
on their order in the register set.
Bit 3: Output Stream 2 (OS2)
Bit 2: Output Stream 1 (OS1)
Bit 1: Input Stream 2 (IS2)
Bit 0: Input Stream 1 (IS1)
Table 237. 20h: INTCTL - Interrupt Control Register (Sheet 2 of 2)
Size: 32 bit Default: 0000_0000h Power Well: Core
Access
PCI Configuration B:D:F 0:27:0
Offset Start:
Offset End:
20h
23h
Memory Mapped IO BAR: LBAR Offset:
Bit Range Default Access Acronym Description