Datasheet

Intel
®
High Definition Audio
β
D27:F0
Intel
®
Atom™ Processor E6xx Series Datasheet
165
9.3.2.1.10 Offset 14h: ECAP - Extended Capabilities
9.3.2.1.11 Offset 18h: STRMPAY – Stream Payload Capability Register
9.3.2.1.12 Offset 20h: INTCTL - Interrupt Control Register
Table 235. 14h: ECAP - Extended Capabilities
Size: 32 bit Default: 0000_0000h Power Well: Core
Access
PCI Configuration B:D:F 0:27:0
Offset Start:
Offset End:
14h
17h
Memory Mapped IO BAR: LBAR Offset:
Bit Range Default Access Acronym Description
31 :1 0 RO RSVD Reserved
00h R/WO DS
Docking Supported: A 1 indicates that processor supports Intel
®
HD
Audio
β
Docking. The GCTL.DA bit is only writable when this bit is 1. This
bit is reset to its default value only on RESET_B, but not on a CRST_B or
D3
HOT
-to-D0 transition.
Table 236. 18h: STRMPAY – Stream Payload Capability Register
Size: 32 bit Default: 0018_0030h Power Well: Core
Access
PCI Configuration B:D:F 0:27:0
Offset Start:
Offset End:
18h
1Bh
Memory Mapped IO BAR: LBAR Offset:
Bit Range Default Access Acronym Description
31 :24 0 RO RSVD Reserved
23 :16 18h RO IN
Input: Indicates the number of words per frame for the input streams is
24 words. This measurement is in 16 bit word quantities per 48kHz
frame.
15 :08 0 RO RSVD Reserved
07 :00 30h RO OUT
Output: Indicates the number of words per frame for output streams is
48 words. This measurement is in 16-bit word quantities per 48kHz
frame.
Table 237. 20h: INTCTL - Interrupt Control Register (Sheet 1 of 2)
Size: 32 bit Default: 0000_0000h Power Well: Core
Access
PCI Configuration B:D:F 0:27:0
Offset Start:
Offset End:
20h
23h
Memory Mapped IO BAR: LBAR Offset:
Bit Range Default Access Acronym Description
31 0 RW GIE
Global Interrupt Enable: Global bit to enable device interrupt
generation. When set to 1 the Intel
®
HD Audio
β
function is enabled to
generate an interrupt. This control is in addition to any bits in the bus
specific address space, such as the Interrupt Enable bit in the PCI
Configuration Space.
Note: This bit is not affected by the D3
HOT
to D0 transition.
30 0 RW CIE
Controller Interrupt Enable: Enables the general interrupt for
controller functions. When set to 1, the controller generates an interrupt
when the corresponding status bit gets set due to a Response Interrupt,
a Response Buffer Overrun, and State Change events.
Note: This bit is not affected by the D3
HOT
to D0 transition.