Datasheet

Intel
®
High Definition Audio
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D27:F0
Intel
®
Atom™ Processor E6xx Series Datasheet
164
9.3.2.1.8 Offset 0Eh: STATESTS – State Change Status
9.3.2.1.9 Offset 10h: GSTS – Global Status
Table 233. 0Eh: STATESTS – State Change Status
Size: 16 bit Default: 0000h Power Well: Core
Access
PCI Configuration B:D:F 0:27:0
Offset Start:
Offset End:
0Eh
0Fh
Memory Mapped IO BAR: LBAR Offset:
Bit Range Default Access Acronym Description
15 :02 0 RO RSVD Reserved
01 :00 0 RWC SDIWAKE
SDIN State Change Status Flags: Flag bits that indicate which SDI
signal(s) received a “State Change” event. The bits are cleared by writing
a 1 to them.
Bit 0 is for SDI0,
Bit 1 is for SDI1
Bit 2 is for SDI2.
These bits are in the suspend well and only cleared on a power-on reset.
Software must not make assumptions about the reset state of these bits
and must set them appropriately.
Table 234. 10h: GSTS – Global Status
Size: 16 bit Default: 0000h Power Well: Core
Access
PCI Configuration B:D:F 0:27:0
Offset Start:
Offset End:
10h
11h
Memory Mapped IO BAR: LBAR Offset:
Bit Range Default Access Acronym Description
15 :04 0 RO RSVD Reserved
03 0 RWC DMIS
Dock Mated Interrupt Status: A 1 indicates that the dock mating or
unmating process has completed. For the docking process it indicates
that dock is electrically isolated and that software may report to the user
that physical undocking may commence. This bit gets set to a 1 by
hardware when the DM bit transitions from a 0 to a 1 (docking) or from a
1 to a 0 (undocking). Note that this bit is set regardless of the state of
the DMIE bit.
Software clears this bit by writing a 1 to it. Writing a 0 to this bit has no
affect.
02 0 RO DM
Dock Mated: This bit effectively communicates to software that an
Intel
®
HD Audio
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docked codec is physically and electrically attached.
Controller hardware sets this bit to 1 after the docking sequence
triggered by writing a 1 to the Dock Attach (GCTL.DA) bit is completed
(HDA_DOCKRST_B deassertion). This bit indicates to software that the
docked codec(s) may be discovered via the STATESTS register and then
enumerated.
Controller hardware sets this bit to 0 after the undocking sequence
triggered by writing a 0 to the Dock Attach (GCTL.DA) bit is completed
(HDA_DOCK_EN_B deasserted). This bit indicates to software that the
docked codec(s) may be physically undocked.
This bit is Read Only. Writes to this bit have no effect.
01 0 RWC FSTS
Flush Status: This bit is set to a 1 by the hardware to indicate that the
flush cycle initiated when the FCNTRL bit (LBAR+08h, bit 1) was set has
completed. Software must write a 1 to clear this bit before the next time
FCNTRL is set.
00 0 RO RSVD Reserved