Datasheet

Intel
®
High Definition Audio
β
D27:F0
Intel
®
Atom™ Processor E6xx Series Datasheet
163
9.3.2.1.7 Offset 0Ch: WAKEEN – Wake Enable
00 0 RW CRST_B
Controller Reset #:
0 = Writing a 0 to this bit causes the Intel
®
HD Audio
β
controller to be
reset. All state machines, FIFO’s and non-resume well memory mapped
configuration registers (not PCI Configuration Registers) in the controller
will be reset. The Intel
®
HD Audio
β
link RESET_B signal will be asserted
and all other link signals will be driven to their default values. After the
hardware has completed sequencing into the reset state, it will report a 0
in this bit. Software must read a 0 from this bit to verify that the
controller is in reset.
1 = Writing a 1 to this bit causes the controller to exit its reset state and
deassert the Intel
®
HD Audio
β
link RESET_B signal. Software is
responsible for setting/clearing this bit such that the minimum Intel
®
HD
Audio
β
link RESET_B signal assertion pulse width specification is
met. When the controller hardware is ready to begin operation, it will
report a 1 in this bit. Software must read a 1 from this bit before
accessing any controller registers. This bit defaults to a 0 after hardware
reset, therefore, software needs to write a 1 to this bit to begin
operation.
Notes:
The CORB/RIRB RUN bits and all Stream RUN bits must be verified
cleared to zero before writing a 0 to this bit in order to assure a clean
restart.
When setting or clearing this bit, software must ensure that minimum
link timing requirements (minimum RESET_B assertion time, etc.) are
met.
When this bit is 0 indicating that the controller is in reset, writes to all
Intel
®
HD Audio
β
memory mapped registers are ignored as if the device
is not present. The only exception is the this register itself. The Global
Control register is write-able as a DWord, Word, or Byte even when
CRST_B (this bit) is 0 if the byte enable for the byte containing the
CRST_B bit (Byte Enable 0) is active. If Byte Enable 0 is not active, writes
to the Global Control register will be ignored when CRST_B is 0. When
CRST_B is 0, reads to Intel
®
HD Audio
β
memory mapped registers will
return their default value except for registers that are not reset with
RESET_B or on a D3hot -> D0 transition.
Table 232. 0Ch: WAKEEN – Wake Enable
Size: 16 bit Default: 0000h Power Well: Core
Access
PCI Configuration B:D:F 0:27:0
Offset Start:
Offset End:
0Ch
0Dh
Memory Mapped IO BAR: LBAR Offset:
Bit Range Default Access Acronym Description
15 :02 0 RO RSVD Reserved
01 :00
0
RW,
SUS
SDIWEN
SDIN Wake Enable Flags (SDIWEN): These bits control which SDI
signal(s) may generate a wake event. A 1 in the bit mask indicates that
the associated SDIN signal is enabled to generate a wake.
Bit 0 is for SDI0,
Bit 1 is for SDI1
These bits are in the suspend well and only cleared on a power-on reset.
Software must not make assumptions about the reset state of these bits
and must set them appropriately.
Table 231. 08h: GCTL – Global Control (Sheet 2 of 2)
Size: 32 bit Default: 0000_0000h Power Well: Core
Access
PCI Configuration B:D:F 0:27:0
Offset Start:
Offset End:
08h
0Bh
Memory Mapped IO BAR: LBAR Offset:
Bit Range Default Access Acronym Description