Datasheet

Intel
®
High Definition Audio
β
D27:F0
Intel
®
Atom™ Processor E6xx Series Datasheet
162
9.3.2.1.6 Offset 08h: GCTL – Global Control
06 :00 1Dh RO INPAY
Input Payload Capability: Indicates the total input payload available
on the link. This does not include bandwidth used for response. This
measurement is in 16-bit word quantities per 48 kHz frame. The default
link clock speed of 24.000 MHz provides 500 bits per frame, or 31.25
words in total. 36 bits are used for response, leaving 29 words for data
payload.
00h: 0 words
01h: 1 word payload
…
FFh: 255h word payload
Table 231. 08h: GCTL – Global Control (Sheet 1 of 2)
Size: 32 bit Default: 0000_0000h Power Well: Core
Access
PCI Configuration B:D:F 0:27:0
Offset Start:
Offset End:
08h
0Bh
Memory Mapped IO BAR: LBAR Offset:
Bit Range Default Access Acronym Description
31 :09 0 RO RSVD Reserved
08 0 RW UNSOL
Accept Unsolicited Response Enable:
0 = Unsolicited responses from the codecs are not accepted.
1 = Unsolicited response from the codecs are accepted by the controller
and placed into the Response Input Ring Buffer.
07 :02 0 RO RSVD Reserved
01 0 RW FCNTRL
Flush Control: Writing a 1 to this bit initiates a flush. When the flush
completion is received by the controller, hardware sets the Flush Status
bit and clears this Flush Control bit. Before a flush cycle is initiated, the
DMA Position Buffer must be programmed with a valid memory address
by software, but the DMA Position Buffer bit 0 need not be set to enable
the position reporting mechanism. Also, all streams must be stopped (the
associated RUN bit must be 0).
When the flush is initiated, the controller will flush pipelines to memory
to guarantee that the hardware is ready to transition to a D3 state.
Setting this bit is not a critical step in the power state transition if the
content of the FIFOs is not critical.
Table 230. 06h: INPAY – Input Payload Capability Register (Sheet 2 of 2)
Size: 16 bit Default: 001Dh Power Well: Core
Access
PCI Configuration B:D:F 0:27:0
Offset Start:
Offset End:
06h
07h
Memory Mapped IO BAR: LBAR Offset:
Bit Range Default Access Acronym Description