Datasheet

Intel
®
High Definition Audio
β
D27:F0
Intel
®
Atom™ Processor E6xx Series Datasheet
157
9.3.1.46 Offset 140h: L1DESC – Link 1 Description Register
9.3.1.47 Offset 148h: L1ADD – Link 1 Address Register
9.3.2 Memory Mapped Configuration Registers
9.3.2.1 Intel
®
HD Audio
β
Registers
The base memory location for these memory mapped configuration registers is
specified in the LBAR and UBAR (D27:F0 - offset 10h and D27:F0 - offset 14h)
registers. The individual registers are then accessible at LBAR + Offset as indicated in
the following table.
15 :08 01h RO LNKENT
Number of Link Entries: The Intel
®
HD Audio
β
controller only connects
to one device, the processor egress port. Therefore this field reports a
value of 1h.
07 :04 0h RO RSVD Reserved
03 :00 0h RO ELTYP
Element Type: The Intel
®
HD Audio
β
controller is an Integrated Root
Complex Device. Therefore this field reports a value of 0h.
Table 223. 140h: L1DESC – Link 1 Description Register
Size: 32 bit Default: 0000_0001 Power Well: Core
Access
PCI Configuration B:D:F 0:27:0
Offset Start:
Offset End:
140h
143h
Bit Range Default Access Acronym Description
31 :24 00h RO TPORT
Target Port Number: The Intel
®
HD Audio
β
controller targets the
processor RCRB egress port, which is port _B0.
23 :16 Variable RO TCOMPID
Target Component ID: This field returns the value of the ESD.COMPID
field of the chip configuration section. ESD.COMPID is programmed by
BIOS.
15 :02 0h RO RSVD Reserved
01 0 RO LNKTYP Link Type: Indicates Type 0.
00 1 RO LNKVLD Link Valid: Hardwired to 1.
Table 224. 148h: L1ADD – Link 1 Address Register
Size: 32 bit Default: Variable Power Well: Core
Access
PCI Configuration B:D:F 0:27:0
Offset Start:
Offset End:
148h
14Bh
Bit Range Default Access Acronym Description
31 :14 Variable RW
RCBA
R/W
Base (BASE): Hardwired to match the RCBA register value in the PCI-
LPC bridge (D31:F0h).
13 :00 0h RO RSVD Reserved
Table 222. 134h: ESD – Element Self Description Register (Sheet 2 of 2)
Size: 32 bit Default: 0F00_0100h Power Well: Core
Access
PCI Configuration B:D:F 0:27:0
Offset Start:
Offset End:
134h
137h
Bit Range Default Access Acronym Description