Datasheet
Intel
®
High Definition Audio
β
D27:F0
Intel
®
Atom™ Processor E6xx Series Datasheet
156
9.3.1.43 Offset 126h: VC1STS – VC1 Resource Status Register
9.3.1.44 Offset 130h: RCCAP – Root Complex Link Declaration Enhanced
Capability Header Register
9.3.1.45 Offset 134h: ESD – Element Self Description Register
23 :08 0 RO RSVD Reserved
07 :00 00h RW/RO
TC/VC Map: This field indicates the TCs that are mapped to the VC1
resource. Bit 0 is hardwired to 0 indicating it can not be mapped to VC1.
Bits [7:1] are implemented as RW bits. This field is not used by the
processor, but it is RW to avoid confusing software.
Table 220. 126h: VC1STS – VC1 Resource Status Register
Size: 16 bit Default: 0000h Power Well: Core
Access
PCI Configuration B:D:F 0:27:0
Offset Start:
Offset End:
126h
127h
Bit Range Default Access Acronym Description
15 :00 0 RO RSVD Reserved
Table 221. 130h: RCCAP – Root Complex Link Declaration Enhanced Capability Header
Register
Size: 32 bit Default: 0001_0005h Power Well: Core
Access
PCI Configuration B:D:F 0:27:0
Offset Start:
Offset End:
130h
133h
Bit Range Default Access Acronym Description
31 :20 000h RO NXTCAP Next Capability Offset: Indicates this is the last capability.
19 :16 1h RO Capability Version
15 :00 0005h RO PCI Express* Extended Capability ID
Table 222. 134h: ESD – Element Self Description Register (Sheet 1 of 2)
Size: 32 bit Default: 0F00_0100h Power Well: Core
Access
PCI Configuration B:D:F 0:27:0
Offset Start:
Offset End:
134h
137h
Bit Range Default Access Acronym Description
31 :24 0Fh RO PORT Port Number: Intel
®
HD Audio
β
assigned as Port _B15.
23 :16 00h RO COMPID
Component ID: This field returns the value of the ESD.CID field of the
chip configuration section. ESD.CID is programmed by BIOS.
Table 219. 120h: VC1CTL – VC1 Resource Control Register (Sheet 2 of 2)
Size: 32 bit Default: 0000_0000h Power Well: Core
Access
PCI Configuration B:D:F 0:27:0
Offset Start:
Offset End:
120h
123h
Bit Range Default Access Acronym Description