Datasheet

Intel
®
High Definition Audio
β
D27:F0
Intel
®
Atom™ Processor E6xx Series Datasheet
155
9.3.1.39 Offset 114h: VC0CTL – VC0 Resource Control Register
9.3.1.40 Offset 11Ah: VC0STS – VC0 Resource Status Register
9.3.1.41 Offset 11Ch: VC1CAP – VC1 Resource Capability Register
9.3.1.42 Offset 120h: VC1CTL – VC1 Resource Control Register
Table 216. 114h: VC0CTL – VC0 Resource Control Register
Size: 32 bit Default: 8000 00FFh Power Well: Core
Access
PCI Configuration B:D:F 0:27:0
Offset Start:
Offset End:
114h
117h
Bit Range Default Access Acronym Description
31 1 RO VC0EN VC0 Enable: Hardwired to 1 for VC0.
30 :08 0 RO RSVD Reserved
07 :00 FFh RW/RO VC0MAP
TC/VC0 Map: Bit 0 is hardwired to 1 since TC0 is always mapped to
VC0. Bits [7:1] are implemented as RW bits.
Table 217. 11Ah: VC0STS – VC0 Resource Status Register
Size: 16 bit Default: 0000h Power Well: Core
Access
PCI Configuration B:D:F 0:27:0
Offset Start:
Offset End:
11Ah
11Bh
Bit Range Default Access Acronym Description
15 :00 0 RO RSVD Reserved
Table 218. 11Ch: VC1CAP – VC1 Resource Capability Register
Size: 32 bit Default: 0000_0000h Power Well: Core
Access
PCI Configuration B:D:F 0:27:0
Offset Start:
Offset End:
11Ch
11Fh
Bit Range Default Access Acronym Description
31 :00 0 RO RSVD Reserved
Table 219. 120h: VC1CTL – VC1 Resource Control Register (Sheet 1 of 2)
Size: 32 bit Default: 0000_0000h Power Well: Core
Access
PCI Configuration B:D:F 0:27:0
Offset Start:
Offset End:
120h
123h
Bit Range Default Access Acronym Description
31 0 RW VC1EN
VC1 Enable:
0 = VC1 is disabled
1 = VC1 is enabled
Note: This bit is not reset on D3
HOT
to D1 transition.
30 :27 0 RO RSVD Reserved
26 :24 000 RW VC1ID
VC1 ID: This field assigns a VC ID to the VC1 resource. This field is not
used by the processor, but it is RW to avoid confusing software.