Datasheet

Intel
®
High Definition Audio
β
D27:F0
Intel
®
Atom™ Processor E6xx Series Datasheet
153
9.3.1.33 Offset 100h: VCCAP – Virtual Channel Enhanced Capability Header
9.3.1.34 Offset 104h: PVCCAP1 – Port VC Capability Register 1
02 0 RW GCD
Clock Gating Disable:
0 = Clock gating within the device is enabled (Default)
1 = Clock gating within the device is disabled.
01 0 RW MD
MSI Disable:
0 = The MSI capability is visible. The NXT_PTR2 register will contain 60h.
1 = The MSI capability is disabled. The NXT_PTR2 register will contain
00h, indicating it’s the last capability in the list.
00 0 RW D
Disable:
1 = D27:F0 is disabled.
Table 210. 100h: VCCAP – Virtual Channel Enhanced Capability Header
Size: 32 bit Default: 1301_0002h Power Well: Core
Access
PCI Configuration B:D:F 0:27:0
Offset Start:
Offset End:
100h
103h
Bit Range Default Access Acronym Description
31 :20 130h RO NXTCAP
Next Capability Offset: Points to the next capability header, which is
the Root Complex Link Declaration Enhanced Capability Header
19 :16 1h RO Capability Version
15 :00 0002h RO PCI Express* Extended Capability
Table 211. 104h: PVCCAP1 – Port VC Capability Register 1
Size: 32 bit Default: 0000_0001h Power Well: Core
Access
PCI Configuration B:D:F 0:27:0
Offset Start:
Offset End:
104h
107h
Bit Range Default Access Acronym Description
31 :03 0 RO RSVD Reserved
02 :00 001 RO VCCNT
Extended VC Count: Indicates that one extended VC (in addition to
VC0) is supported by the Intel
®
HD Audio
β
controller.
Table 209. FCh – FD: Function Disable Register (Sheet 2 of 2)
Size: 32 bit Default: 0000_0000h Power Well: Core
Access
PCI Configuration B:D:F 0:27:0
Offset Start:
Offset End:
FCh
FFh
Bit Range Default Access Acronym Description