Datasheet

Intel
®
High Definition Audio
β
D27:F0
Intel
®
Atom™ Processor E6xx Series Datasheet
152
9.3.1.31 Offset 7Ah: DEVS – Device Status Register
9.3.1.32 Offset FCh – FD: Function Disable Register
14 :12 000 RO MRRS
Max Read Request Size: Hardwired to 000 enabling 128 B maximum
read request size.
11 1 RW NSNPEN
Enable No Snoop:
0 = The Intel
®
HD Audio
β
controller will not set the No Snoop bit. In this
case, isochronous transfers will not use VC1 (VCi) even if it is enabled
since VC1 is never snooped. Isochronous transfers will use VC0.
1 = The Intel
®
HD Audio
β
controller is permitted to set the No Snoop bit
in the Requester Attributes of a bus master transaction. In this case, VC0
or VC1 may be used for isochronous transfers.
Note: This bit is not reset on D3
HOT
to D0 transition.
10 :04 0 RO RSVD Reserved
03 0 RW URREN
Unsupported Request Reporting Enable: Functionality not
implemented. This bit is RW to pass PCIe* compliance testing.
02 0 RW FEREN
Fatal Error Reporting Enable: Functionality not implemented. This bit
is RW to pass PCIe* compliance testing.
01 0 RW NFEREN
Non-Fatal Error Reporting Enable: Functionality not implemented.
This bit is RW to pass PCIe* compliance testing.
00 0 RW CEREN
Correctable Error Reporting Enable: Functionality not implemented.
This bit is RW to pass PCIe* compliance testing.
Table 208. 7Ah: DEVS – Device Status Register
Size: 16 bit Default: 0000h Power Well: Core
Access
PCI Configuration B:D:F 0:27:0
Offset Start:
Offset End:
7Ah
7Bh
Bit Range Default Access Acronym Description
15 :06 0 RO RSVD Reserved
05 0 RO TXP
Transactions Pending:
0 = Completions for all Non-Posted Requests have been received.
1 = The Intel
®
HD Audio
β
controller has issued Non-Posted requests
which have not been completed.
04 :00 0 RO RSVD Reserved
Table 209. FCh – FD: Function Disable Register (Sheet 1 of 2)
Size: 32 bit Default: 0000_0000h Power Well: Core
Access
PCI Configuration B:D:F 0:27:0
Offset Start:
Offset End:
FCh
FFh
Bit Range Default Access Acronym Description
31 :03 0 RO RSVD Reserved
Table 207. 78h: DEVC – Device Control (Sheet 2 of 2)
Size: 16 bit Default: 0800h Power Well: Core
Access
PCI Configuration B:D:F 0:27:0
Offset Start:
Offset End:
78h
79h
Bit Range Default Access Acronym Description