Datasheet

Intel
®
High Definition Audio
β
D27:F0
Intel
®
Atom™ Processor E6xx Series Datasheet
151
9.3.1.27 Offset 70h: PCIE_CAPID – PCI Express* Capability Identifiers Register
9.3.1.28 Offset 72h: PCIECAP – PCI Express* Capabilities Register
9.3.1.29 Offset 74h: DEVCAP – Device Capabilities Register
9.3.1.30 Offset 78h: DEVC – Device Control
Table 204. 70h: PCIE_CAPID – PCI Express* Capability Identifiers Register
Size: 16 bit Default: 10h Power Well: Core
Access
PCI Configuration B:D:F 0:27:0
Offset Start:
Offset End:
70h
71h
Bit Range Default Access Acronym Description
15 :08
60h/00
h
RO NEXT
Next Capability: Defaults to 60h, the address of the next capability
structure in the list.
However, if the FD.MD bit is set, the MSI capability will be disabled and
this register will report 00h indicating this capability is the last capability
in the list.
07 :00 10h RO CAP Cap ID: Indicates that this pointer is a PCI Express* capability structure.
Table 205. 72h: PCIECAP – PCI Express* Capabilities Register
Size: 16 bit Default: 0091h Power Well: Core
Access
PCI Configuration B:D:F 0:27:0
Offset Start:
Offset End:
72h
73h
Bit Range Default Access Acronym Description
15 :08 00 RO RO Reserved
07 :04 1001 RO
Device/Port Type: Indicates that this is a Root Complex Integrated
Endpoint Device.
03 :00 0001 RO RO Capability Version: Indicates version 1.0a PCI Express* capability
Table 206. 74h: DEVCAP – Device Capabilities Register
Size: 32 bit Default: 0000_0000h Power Well: Core
Access
PCI Configuration B:D:F 0:27:0
Offset Start:
Offset End:
74h
77h
Bit Range Default Access Acronym Description
31 :00 0 RO RSVD Reserved
Table 207. 78h: DEVC – Device Control (Sheet 1 of 2)
Size: 16 bit Default: 0800h Power Well: Core
Access
PCI Configuration B:D:F 0:27:0
Offset Start:
Offset End:
78h
79h
Bit Range Default Access Acronym Description
15 0 RO RSVD Reserved