Datasheet

Intel
®
High Definition Audio
β
D27:F0
Intel
®
Atom™ Processor E6xx Series Datasheet
149
9.3.1.22 Offset 54h: PM_CTL_STS - Power Management Control And Status
Register
10 :03 0 RO RSVD Reserved
02 :00 010 RO VS
Version: Indicates support for Revision 1.1 of the PCI Power
Management Specification.
Table 199. 54h: PM_CTL_STS - Power Management Control And Status Register
Size: 32 bit Default: 0000h Power Well: Core
Access
PCI Configuration B:D:F 0:27:0
Offset Start:
Offset End:
54h
57h
Bit Range Default Access Acronym Description
31 :16 0 RO RSVD Reserved
15 0 RWC PMES
PME Status:
0 = Software clears the bit by writing a 1 to it.
1 = This bit is set when the Intel
®
HD Audio
β
controller would normally
assert the PME_B signal independent of the state of the PME_EN bit (bit 8
in this register)
14 :09 0 RO RSVD Reserved
08 0 RW PMEE
PME Enable:
0= Disable
1 = If corresponding PMES also set, the Intel
®
HD Audio
β
controller sets
the generates an internal power management event.
07 :02 0 RO RSVD Reserved
01 :00 00 RO PS
Power State: This field is used both to determine the current power
state of the Intel
®
HD Audio
β
controller and to set a new power state.
The values are:
00 = D0 state
11 = D3
HOT
state
Others = Reserved
Notes:
If software attempts to write a value of 01b or 10b in to this field, the
write operation must complete normally; however, the data is discarded
and no state change occurs.
When in the D3
HOT
states, the Intel
®
HD Audio
β
controller’s configuration
space is available, but the I/O and memory spaces are not. Additionally,
interrupts are blocked.
When software changes this value from the D3
HOT
state to the D0 state,
an internal warm (soft) reset is generated, and software must re-initialize
the function.
Table 198. 52h: PM_CAP – Power Management Capabilities Register (Sheet 2 of 2)
Size: 16 bit Default: 4802h Power Well: Core
Access
PCI Configuration B:D:F 0:27:0
Offset Start:
Offset End:
52h
53h
Bit Range Default Access Acronym Description