Datasheet

Intel
®
High Definition Audio
β
D27:F0
Intel
®
Atom™ Processor E6xx Series Datasheet
148
9.3.1.19 Offset 4Dh – DCKSTS—Docking Status Register
9.3.1.20 Offset 50h: PM_CAPID - PCI Power Management Capability ID
Register
9.3.1.21 Offset 52h: PM_CAP – Power Management Capabilities Register
Table 196. 4Dh: DCKSTS – Docking Status Register
Size: 8 bit Default: 80h Power Well: Core
Access
PCI Configuration B:D:F 0:27:0
Offset Start:
Offset End:
4Dh
4Dh
Bit Range Default Access Acronym Description
07 1 RWO DS
Docking Supported: A 1 indicates that the processor supports Intel
®
HD Audio
β
Docking. The DCKCTL.DA bit is only writable when this DS bit
is 1. Intel
®
HD Audio
β
driver software should only branch to its docking
routine when this DS bit is 1. BIOS may clear this bit to 0 to prohibit the
Intel
®
HD Audio
β
driver software from attempting to run the docking
routines.
Note that this bit is reset to its default value only on a RESET_B, but not
on a CRST_B or D3hot-to-D0 transition.
06 :01 0 RO RSVD Reserved
00 0 RO DM
Dock Mated: This bit effectively communicates to software that an
Intel
®
HD Audio
β
docked codec is physically and electrically attached.
Controller hardware sets this bit to 1 after the docking sequence
triggered by writing a 1 to the Dock Attach (DCKCTL.DA) bit is completed
(HDA_DOCKRST_B deassertion). This bit indicates to software that the
docked codec(s) may be discovered via the STATESTS register and then
enumerated.
Controller hardware sets this bit to 0 after the undocking sequence
triggered by writing a 0 to the Dock Attach (DCKCTL.DA) bit is completed
(HDA_DOCK_EN_B deasserted). This bit indicates to software that the
docked codec(s) may be physically undocked.
Note that this bit is reset on RST_B. It is not directly reset on CRST_B,
however because the dock state machine is reset on CRST_B and the
dock will be electrically isolated, this DM bit will be read as ‘0’ reflecting
the undocked state.
This bit is Read Only. Writes to this bit have no effect.
Table 197. 50h: PM_CAPID - PCI Power Management Capability ID Register
Size: 16 bit Default: 7001h Power Well: Core
Access
PCI Configuration B:D:F 0:27:0
Offset Start:
Offset End:
50h
51h
Bit Range Default Access Acronym Description
15 :08 70h RO NEXT Next Capability: Points to the next capability structure (PCI Express*).
07 :00 01h RO CAP Cap ID: Indicates that this pointer is a PCI power management capability
Table 198. 52h: PM_CAP – Power Management Capabilities Register (Sheet 1 of 2)
Size: 16 bit Default: 4802h Power Well: Core
Access
PCI Configuration B:D:F 0:27:0
Offset Start:
Offset End:
52h
53h
Bit Range Default Access Acronym Description
15 :11 01001 RO
PME Support: Indicates PME_B can be generated from D3
HOT
and D0
states.