Datasheet
Intel
®
High Definition Audio
β
D27:F0
Intel
®
Atom™ Processor E6xx Series Datasheet
147
9.3.1.16 Offset 3Dh – INTPN—Interrupt Pin Register
9.3.1.17 Offset 40h – HDCTL— Intel
®
High Definition Audio
β
Control Register
9.3.1.18 Offset 4Ch – DCKCTL—Docking Control Register
Table 193. 3Dh – INTPN — Interrupt Pin Register
Size: 8 bit Default: Variable Power Well: Core
Access
PCI Configuration B:D:F 0:27:0
Offset Start:
Offset End:
3Dh
3Dh
Bit Range Default Access Acronym Description
07 :04 0 RO RSVD Reserved
03 :00 0 RO
Interrupt Pin: This reflects the value of D27IP.ZIP (Chipset Config
Registers: Offset 3110h:bits 3:0).
Table 194. 40h – HDCTL— Intel
®
High Definition Audio
β
Control Register
Size: 8 bit Default: 00h Power Well: Core
Access
PCI Configuration B:D:F 0:27:0
Offset Start:
Offset End:
40h
40h
Bit Range Default Access Acronym Description
07 :01 0 RO RSVD Reserved
00 0 RO LMVE
Low Voltage Mode Enable:
LVM is not supported.
0 = The Intel
®
HD Audio
β
controller operates in high voltage mode.
1= The Intel
®
HD Audio
β
controller’s AFE operates in low voltage mode.
Table 195. 4Ch – DCKCTL — Docking Control Register
Size: 8 bit Default: 00h Power Well: Core
Access
PCI Configuration B:D:F 0:27:0
Offset Start:
Offset End:
4Ch
4Ch
Bit Range Default Access Acronym Description
07 :01 0 RO RSVD Reserved
00 0 RW/RO DA
Dock Attach: Software writes a 1 to this bit to initiate the docking
sequence on the HDA_DOCK_EN_B and HDA_DOCKRST_B signals. When
the docking sequence is complete hardware will set the Dock Mated
(DCKSTS.DM) status bit to 1.
Software writes a 0 to this bit to initiate the undocking sequence on the
HDA_DOCK_EN_B and HDA_DOCKRST_B signals. When the undocking
sequence is complete hardware will set the Dock Mated (DCKSTS.DM)
status bit to 0.
Note that software must check the state of the Dock Mated (DCKSTS.DM)
bit prior to writing to the Dock Attach bit. Software shall only change the
DA bit from 0 to 1 when DM=0. Likewise, software shall only change the
DA bit from 1 to 0 when DM=1. If these rules are violated, the results are
undefined.
Note that this bit is reset on RESET_B. This bit is not reset on CRST_B.
Note that this bit is Read Only when the DCKSTS.DS bit = 0.