Datasheet

Intel
®
High Definition Audio
β
D27:F0
Intel
®
Atom™ Processor E6xx Series Datasheet
146
9.3.1.13 Offset 2Eh: SID—Subsystem Identifier
This register should be implemented for any function that could be instantiated more
than once in a given system, for example, a system with 2 audio subsystems, one
down on the motherboard and the other plugged into a PCI expansion slot. The SID
register, in combination with the Subsystem Vendor ID register make it possible for the
operating environment to distinguish one audio subsystem from the other.
Software (BIOS) will write the value to this register. After that, the value can be read,
but writes to the register will have no effect. The write to this register should be
combined with the write to the SVID to create one 32-bit write. This register is not
affected by D3
HOT
to D0 reset.
9.3.1.14 Offset 34h – CAP_PTR – Capabilities Pointer Register
9.3.1.15 Offset 3Ch – INTLN: Interrupt Line Register
Table 190. 2Eh: SID—Subsystem Identifier
Size: 16 bit Default: 0000h Power Well: Core
Access
PCI Configuration B:D:F 0:27:0
Offset Start:
Offset End:
2Eh
2Fh
Bit Range Default Access Acronym Description
15 :00 0000h RWO SID Subsystem ID: These RWO bits have no functionality.
Table 191. 34h – CAP_PTR – Capabilities Pointer Register
Size: 8 bit Default: 50h Power Well: Core
Access
PCI Configuration B:D:F 0:27:0
Offset Start:
Offset End:
34h
34h
Bit Range Default Access Acronym Description
07 :00 50h RO SID
Capability Pointer: Indicates that the first capability pointer offset is
offset 50h (Power Management Capability).
Table 192. 3Ch – INTLN: Interrupt Line Register
Size: 8 bit Default: 00h Power Well: Core
Access
PCI Configuration B:D:F 0:27:0
Offset Start:
Offset End:
3Ch
3Ch
Bit Range Default Access Acronym Description
07 :00 00h RW
Interrupt Line: The processor does not use this field directly. It is used
to communicate to software the interrupt line that the interrupt pin is
connected to.