Datasheet

Intel
®
High Definition Audio
β
D27:F0
Intel
®
Atom™ Processor E6xx Series Datasheet
145
9.3.1.11 Offset 14h: UBAR – Upper Base Address Register
9.3.1.12 Offset 2Ch: SVID—Subsystem Vendor Identifier
This register should be implemented for any function that could be instantiated more
than once in a given system, for example, a system with 2 audio subsystems, one
down on the motherboard and the other plugged into a PCI expansion slot, should have
the SVID register implemented. The SVID register, in combination with the Subsystem
ID register, enables the operating environment to distinguish one audio subsystem
from the other.
Software (BIOS) will write the value to this register. After that, the value can be read,
but writes to the register will have no effect. The write to this register should be
combined with the write to the SID to create one 32-bit write. This register is not
affected by D3
HOT
to D0 reset.
Table 187. 10h: LBAR – Lower Base Address Register
Size: 32 bit Default: 00000004h Power Well: Core
Access
PCI Configuration B:D:F 0:27:0
Offset Start:
Offset End:
10h
13h
Bit Range Default Access Acronym Description
31 :14 0 RW LBA
Lower Base Address: Base address for the Intel
®
HD Audio
β
controller’s memory mapped configuration registers. 16 Kbytes are
requested by hardwiring bits 13:4 to 0’s.
13 :04 0 RO Hardwired to 0.
03 0 RO PREF Prefetchable: Indicates that this BAR is NOT pre-fetchable.
02 :01 10 RO ADDRNG
Address Range: Indicates that this BAR can be located anywhere in 32-
bit address space.
00 0 RO RTE Resource Type:
Indicates that this BAR is located in memory space.
Table 188. 14h: UBAR – Upper Base Address Register
Size: 32 bit Default: 00000000h Power Well: Core
Access
PCI Configuration B:D:F 0:27:0
Offset Start:
Offset End:
14h
17h
Bit Range Default Access Acronym Description
31 :00 0 RW UBA
Upper Base Address: Upper 32 bits of the Base address for the Intel
®
HD Audio
β
controller’s memory mapped configuration registers.
Table 189. 2Ch: SVID—Subsystem Vendor Identifier
Size: 16 bit Default: 0000h Power Well: Core
Access
PCI Configuration B:D:F 0:27:0
Offset Start:
Offset End:
2Ch
2Dh
Bit Range Default Access Acronym Description
15 :00 0000h RWO SVID Subsystem Vendor ID: These RWO bits have no functionality.