Datasheet
Intel
®
High Definition Audio
β
D27:F0
Intel
®
Atom™ Processor E6xx Series Datasheet
144
9.3.1.7 Offset 0Ch: CLS - Cache Line Size Register
9.3.1.8 Offset 0Dh: LT – Latency Timer Register
9.3.1.9 Offset 0Eh: HEADTYP - Header Type Register
9.3.1.10 Offset 10h: LBAR – Lower Base Address Register
This BAR creates 16 Kbytes of memory space to signify the base address of Intel
®
HD
Audio
β
memory mapped configuration registers.
07 :00 00h RO PI
Programming Interface: Indicates Intel
®
HD Audio
β
programming
interface.
Table 184. 0Ch: CLS - Cache Line Size Register
Size: 8 bit Default: 00h Power Well: Core
Access
PCI Configuration B:D:F 0:27:0
Offset Start:
Offset End:
0Ch
0Ch
Bit Range Default Access Acronym Description
07 :00 00h RW CLS
Cache Line Size: Doesn’t apply to PCI Express*. The PCI Express*
specification requires this to be implemented as a RW register but has no
functional impact on the Intel
®
HD Audio
β
controller.
Table 185. 0Dh: LT – Latency Timer Register
Size: 8 bit Default: 00h Power Well: Core
Access
PCI Configuration B:D:F 0:27:0
Offset Start:
Offset End:
0Dh
0Dh
Bit Range Default Access Acronym Description
07 :00 00h RO LT Latency Timer: Doesn’t apply to PCI Express*. Hardwired to 00h.
Table 186. 0Eh: HEADTYP - Header Type Register
Size: 8 bit Default: 00h Power Well: Core
Access
PCI Configuration B:D:F 0:27:0
Offset Start:
Offset End:
0Eh
0Eh
Bit Range Default Access Acronym Description
07 :00 00h RO HEADTYP Header Type: Implements Type 0 Configuration header.
Table 183. 09h: CC – Class Codes Register (Sheet 2 of 2)
Size: 24 bit Default: 040300h Power Well: Core
Access
PCI Configuration B:D:F 0:27:0
Offset Start:
Offset End:
09h
0Bh
Bit Range Default Access Acronym Description