Datasheet

Intel
®
High Definition Audio
β
D27:F0
Intel
®
Atom™ Processor E6xx Series Datasheet
143
9.3.1.4 Offset 06h: PCISTS – PCI Status Register
9.3.1.5 Offset 08h: RID – Revision Identification Register
9.3.1.6 Offset 09h: CC – Class Codes Register
00 0 RO RSVD Reserved
Table 181. 06h: PCISTS – PCI Status Register
Size: 16 bit Default: 0010h Power Well: Core
Access
PCI Configuration B:D:F 0:27:0
Offset Start:
Offset End:
06h
07h
Bit Range Default Access Acronym Description
15 :05 0 RO RSVD Reserved
04 1 RO CAP_LIST
Capabilities List Exists: Hardwired to 1. Indicates that the controller
contains a capabilities pointer list. The first item is pointed to by looking
at configuration offset 34h.
03 0 RO IS
Interrupt Status:
0= This bit is 0 after the interrupt is cleared.
1= This bit is 1 when the INTx_B is asserted.
02 :00 0 RO RSVD Reserved
Table 182. 08h: RID – Revision Identification Register
Size: 8 bit Default: Refer to bit description Power Well: Core
Access
PCI Configuration B:D:F 0:27:0
Offset Start:
Offset End:
08h
08h
Bit Range Default Access Acronym Description
07 :00
Refer to
bit
descript
ion
RO RID
Revision ID: Indicates the device specific revision identifier. For the B-0
Stepping, this value is 01h. For the B-1 Stepping, this value is 02h.
Table 183. 09h: CC – Class Codes Register (Sheet 1 of 2)
Size: 24 bit Default: 040300h Power Well: Core
Access
PCI Configuration B:D:F 0:27:0
Offset Start:
Offset End:
09h
0Bh
Bit Range Default Access Acronym Description
23 :16 04h RO BCC
Base Class Code: This register indicates that the function implements a
multimedia device.
15 :08 03h RO SCC
Sub Class Code: This indicates the device is an Intel
®
HD Audio
β
audio
device, in the context of a multimedia device.
Table 180. 04h: PCICMD – PCI Command Register (Sheet 2 of 2)
Size: 16 bit Default: 0000h Power Well: Core
Access
PCI Configuration B:D:F 0:27:0
Offset Start:
Offset End:
04h
05h
Bit Range Default Access Acronym Description