Datasheet

Intel
®
High Definition Audio
β
D27:F0
Intel
®
Atom™ Processor E6xx Series Datasheet
138
Prior to the physical undocking process the user normally requests undocking. Software
then gracefully halts the streams to the codecs in the docking station and then initiates
the undocking sequence in the Intel
®
HD Audio
β
controller. Intel
®
HD Audio
β
controller
asserts dock reset and then manages the external switch to electrically isolate the dock
codec from the processor’s Intel
®
HD Audio
β
interface prior to physical undocking.
Electrical isolation during surprise undocking is handled external to the Intel
®
HD
Audio
β
controller, and software invokes the undocking sequence in the Intel
®
HD Audio
β
controller as part of the clean-up process simply to prepare for a subsequent docking
event. The Intel
®
HD Audio
β
controller isn’t aware that a surprise undock occurred.
9.2.1 Dock Sequence
Note: This sequence is followed when the system is running and a docking event occurs as
well as when resuming from S3 (RESET_B asserted) and Intel
®
HD Audio
β
controller
D3.
1. Since the processor supports docking, the Docking Supported (DCKSTS. DS) bit
defaults to a 1. Post BIOS and ACPI Software use this bit to determine if the Intel
®
HD Audio
β
controller supports docking. BIOS may write a 0 to this RWO bit during
POST to effectively turn off the docking feature.
2. After reset in the undocked quiescent state, the Dock Attach (DCKCTL.DA) bit and
the Dock Mate (DCKSTS.DM) bit are both de-asserted. The HDA_DOCK_EN_B
signal is de-asserted and HDA_DOCKRST_B is asserted. HDA_CLK, HDA_SYNC and
HDA_SDO signals may or may not be running at the point in time that the docking
event occurs.
3. The physical docking event is signaled to ACPI BIOS software via ACPI control
methods. How this is done is outside the scope of this specification.
4. ACPI BIOS software first checks that the docking is supported via DCKSTS.DS=1
and that the DCKSTS.DM=0 and then initiates the docking sequence by writing a 1
to the DCKCTL.DA bit.
5. The Intel
®
HD Audio
β
controller then asserts the HDA_DOCK_EN_B signal so that
the HDA_CLK signal begins toggling to the dock codec. HDA_DOCK_EN_B shall be
asserted synchronously to HDA_CLK and timed such that HDA_CLK is low,
HDA_SYNC is low, and HDA_SDO is low. The first 8 bits of the Command field are
“reserved” and always driven to 0. This creates a predictable point in time to
always assert HDA_DOCK_EN_B.
6. After the controller asserts HDA_DOCK_EN_B it waits for a minimum of 2400
HDA_CLKs (100 µs) and then de-asserts HDA_DOCKRST_B. This is done in such a
way to meet the Intel
®
HD Audio
β
link reset exit specification. HDA_DOCKRST_B
de-assertion should be synchronous to HDA_CLK and timed such that there are
least four full HDA_CLKs from the de-assertion of HDA_DOCKRST_B to the first
frame HDA_SYNC assertion.
7. The Connect/Turnaround/Address Frame hardware initialization sequence will now
occur on the dock codecs’ HDA_SDI signals. A dock codec is detected when
HDA_SDI is high on the last HDA_CLK cycle of the Frame Sync of a Connect Frame.
The appropriate bit(s) in the State Change Status (STATESTS) register will be set.
The Turnaround and Address Frame initialization sequence then occurs on the dock
codecs’ HDA_SDI(s).
8. After this hardware initialization sequence is complete (approximately 32 frames),
the controller hardware sets the DCKSTS.DM bit to 1 indicating that the dock is now
mated. ACPI BIOS polls the DCKSTS.DM bit and when it detects it is set to 1,
conveys this to the OS through a plug-N-play IRP. This eventually invokes the
Intel
®
HD Audio
β
Bus Driver which then begins it’s codec discovery, enumeration,
and configuration process. Intel
®
HD Audio
β
Bus Driver software “discovers” the
dock codecs by comparing the bits now set in the STATESTS register with the bits
that were set prior to the docking event.