Datasheet

PCI Express*
Intel
®
Atom™ Processor E6xx Series Datasheet
132
8.2.5 Port Configuration
08 0 RW PMEE
PME Enable: The root port takes no action on this bit, but it must be RW
for legacy Microsoft* operating systems to enable PME on devices
connected to this root port.
07 : 02 0 RO RSVD Reserved
01 : 00 00 RW PS
Power State: This field is used both to determine the current power state
of the root port and to set a new power state. The values are:
00 = D0 state
11 = D3
HOT
state
When in D3
HOT
, the port’s configuration space is available, but I/O,
memory, and type 1 configuration cycles are not accepted. Interrupts are
blocked as software disables interrupts prior to placing the port into
D3
HOT
. Writes of ‘10’ or ‘01’ are ignored.
Table 171. Port Configuration
Start End Symbol Register Name
D8 DB MPC Miscellaneous Port Configuration
DC DF SMSCS SMI / SCI Status
Table 170. Offset A4h: PMCS — PCI Power Management Control And Status (Sheet 2 of 2)
Size: 32 bit Default: 00000000h Power Well: Core
Access
PCI Configuration B:D:F 0:23-26:0
Offset Start:
Offset End:
A4h
A7h
Bit Range Default Access Acronym Description