Datasheet

PCI Express*
Intel
®
Atom™ Processor E6xx Series Datasheet
129
8.2.2.12 RCTL — Root Control
8.2.2.13 RCAP — Root Capabilities
8.2.2.14 RSTS — Root Status
Table 161. Offset 5Ch: RCTL — Root Control
Size: 16 bit Default: 0000h Power Well: Core
Access
PCI Configuration B:D:F 0:23-26:0
Offset Start:
Offset End:
5Ch
5Bh
Bit Range Default Access Acronym Description
15 : 04 0 RO RSVD Reserved
03 0 RW PIE
PME Interrupt Enable: When set, this enables interrupt generation
when RSTS.PS is in a set state (either due to a ‘0’ to ‘1’ transition, or due
to this bit being set with RSTS.PS already set).
02 0 RW SFE
SERR_B on FE Enable: When set, SERR_B is generated if a fatal error is
reported on this port, including fatal errors in this port. This bit is not
dependant on CMD.SEE being set.
01 0 RW SNE
SERR_B on NFE Enable: When set, SERR_B is generated if a non-fatal
error is reported on the port, including non-fatal errors in the port. This
bit is not dependant on CMD.SEE being set.
00 0 RW SCE
SERR_B on CE Enable: When set, SERR_B is generated if a correctable
error is reported on this port, including correctable errors in this port.
This bit is not dependant on CMD.SEE being set.
Table 162. Offset 5Eh: RCAP — Root Capabilities
Size: 16 bit Default: 0000h Power Well: Core
Access
PCI Configuration B:D:F 0:23-26:0
Offset Start:
Offset End:
5Eh
5Fh
Bit Range Default Access Acronym Description
15 : 01 0 RO RSVD Reserved
00 0 RO CSV
CRS Software Visibility: This bit is not supported by the processor. This
bit, when set, indicates that the Root Port is capable of returning
Configuration Request Retry Status (CRS) Completion Status to software.
Table 163. Offset 60h: RSTS — Root Status
Size: 32 bit Default: 00000000h Power Well: Core
Access
PCI Configuration B:D:F 0:23-26:0
Offset Start:
Offset End:
60h
63h
Bit Range Default Access Acronym Description
31 : 18 0 RO RSVD Reserved
17 0 RO PP PME Pending: This will never be set by the processor.
16 0 RWC PS
PME Status: This indicates that PME was asserted by the requestor ID in
RID. Subsequent PMEs are kept pending until this bit is cleared.
15 : 00 0 RO RID
PME Requestor ID: This indicates the PCI requestor ID of the last PME
requestor. Valid only when PS is set. Root ports are capable of storing the
requester ID for two PM_PME messages, with one active (this register)
and a one deep pending queue. Subsequent PM_PME messages will be
dropped.