Datasheet

PCI Express*
Intel
®
Atom™ Processor E6xx Series Datasheet
128
8.2.2.11 SLSTS — Slot Status
03 0b RW PDE
Presence Detect Changed Enable: When set, enables the generation
of a hot plug interrupt or wake message when the presence detect logic
changes state.
02 0b RO MSE
MRL Sensor Changed Enable: MSE is not supported, but it is
read/write for ease of implementation and to easily draft off of the PCI
Express* specification.
01 0b RW PFE
Power Fault Detected Enable: PFE is not supported, but is it is
read/write for ease of implementation and to easily draft off of the PCI
Express* specification.
00 0b RW ABE
Attention Button Pressed Enable: ABE is not supported, but it is
read/write for ease of implementation and to easily draft off of the PCI
Express* specification.
Table 160. Offset 5Ah: SLSTS — Slot Status
Size: 16 bit Default: 0000h Power Well: Core
Access
PCI Configuration B:D:F 0:23-26:0
Offset Start:
Offset End:
5Ah
5Bh
Bit Range Default Access Acronym Description
15 : 09 0 RO RSVD Reserved
08 0 RWC LASC
Link Active State Changed: This bit is set when the value reported in
the Data Link Layer Link Active field of the Link Status register is
changed. In response to a Data Link Layer State Changed event,
software must read the Data Link Layer Link Active field of the Link
Status register to determine if the link is active before initiating
configuration cycles to the hot plugged device.
07 0 RO RSVD Reserved
06 0 RO PDS
Presence Detect State: If XCAP.SI is set (indicating that this root port
spawns a slot), this bit indicates whether a device is connected (‘1’) or
empty (‘0’). If XCAP.SI is cleared, this bit is a ‘1.’
05 0 RO MS MRL Sensor State: Reserved as the MRL sensor is not implemented
04 0 RO RSVD Reserved
03 0 RWC PDC
Presence Detect Changed: This bit is set by the root port when the
PDS bit changes state.
02 0 RO MSC MRL Sensor Changed: Reserved as the MRL sensor is not implemented
01 0 RO PFD
Power Fault Detected: Reserved as a power controller is not
implemented
00 0 RO ABP
Attention Button Pressed: Reserved as Attention Button Pressed is not
implemented
Table 159. Offset 58h: SLCTL — Slot Control (Sheet 2 of 2)
Size: 16 bit Default: 0000h Power Well: Core
Access
PCI Configuration B:D:F 0:23-26:0
Offset Start:
Offset End:
58h
59h
Bit Range Default Access Acronym Description